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ADIN1110CCPZ-R7 数据表(PDF) 85 Page - Analog Devices |
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ADIN1110CCPZ-R7 数据表(HTML) 85 Page - Analog Devices |
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85 / 107 page  Data Sheet ADIN1110 REGISTERS analog.com Rev. B | 85 of 107 BASE-T1 Autonegotiation Link Partner Base Page Ability Register, Bits[31:16] Device Address: 0x07; Register Address: 0x0206, Reset: 0x0000, Name: AN_LP_ADV_ABILITY_M This address corresponds to the link partner's BASE-T1 autonegotiation base page ability register, Bits[31:16], specified in Clause 45.2.7.22 of Standard 802.3. Note that the value of this register is latched when the AN_LP_ADV_ABILITY_L register is read. Reading this register returns the latched value rather than the current value. Table 155. Bit Descriptions for AN_LP_ADV_ABILITY_M Bits Bit Name Description Reset Access 15 RESERVED Reserved. 0x0 R 14 AN_LP_ADV_B10L Link Partner 10BASE-T1L Ability. This bit indicates if the link partner has 10BASE-T1L ability. 0x0 R [13:8] RESERVED Reserved. 0x0 R 7 AN_LP_ADV_B1000 Link Partner 1000BASE-T1 Ability. This bit indicates if the link partner has 1000BASE-T1 ability. 0x0 R 6 AN_LP_ADV_B10S_FD Link Partner 10BASE-T1S Full Duplex Ability. This bit indicates if the link partner has 10BASE- T1S ability. 0x0 R 5 AN_LP_ADV_B100 Link Partner 100BASE-T1 Ability. This bit indicates if the link partner has 100BASE-T1 ability. 0x0 R 4 AN_LP_ADV_MST Link Partner Master/Slave Configuration. This bit reports the master/slave configuration of the link partner, as follows: 0: slave, 1: master. See also the AN_LP_ADV_FORCE_MS bit, which determines whether this bit expresses a preference or a forced value. See IEEE Standard 802.3 Subclause 98.2.1.2.3 (master/slave configuration is Bit 4 of the transmitted nonce field). 0x0 R [3:0] RESERVED Reserved. 0x0 R BASE-T1 Autonegotiation Link Partner Base Page Ability Register, Bits[47:32] Device Address: 0x07; Register Address: 0x0207, Reset: 0x0000, Name: AN_LP_ADV_ABILITY_H This address corresponds to the link partner's BASE-T1 autonegotiation base page ability register, Bits[47:32], specified in Clause 45.2.7.22 of Standard 802.3. Note that the value of this register is latched when the AN_LP_ADV_ABILITY_L register is read. Reading this register returns the latched value rather than the current value. Table 156. Bit Descriptions for AN_LP_ADV_ABILITY_H Bits Bit Name Description Reset Access 15 RESERVED Reserved. 0x0 R 14 AN_LP_ADV_B10L_EEE Link Partner 10BASE-T1L EEE Ability. This bit reports if the link partner is capable of using 10BASE-T1L energy efficient Ethernet. 0x0 R 13 AN_LP_ADV_B10L_TX_LVL_HI_ABL Link Partner 10BASE-T1L High Level Transmit Operating Mode Ability. This bit reports whether the link partner is capable of transmitting in the high level (2.4 V p-p) transmit operating mode. This bit is used with AN_LP_ADV_B10L_TX_LVL_HI_REQ to configure the 10BASE-T1L transmission level (2.4 V p-p or 1.0 V p-p); see the AN_ADV_B10L_TX_LVL_HI_REQ bit for more details. 0x0 R 12 AN_LP_ADV_B10L_TX_LVL_HI_REQ Link Partner 10BASE-T1L High Level Transmit Operating Mode Request. This bit reports whether the link partner is requesting that the high level (2.4 V p-p) transmit operating mode be used. See the AN_ADV_B10L_TX_LVL_HI_REQ bit for more details. 0x0 R 11 AN_LP_ADV_B10S_HD Link Partner 10BASE-T1S Half-Duplex Ability. This bit reports if the link partner is capable of using 10BASE-T1S half duplex. 0x0 R [10:0] RESERVED Reserved. 0x0 R BASE-T1 Autonegotiation Next Page Transmit Register, Bits[15:0] Device Address: 0x07; Register Address: 0x0208, Reset: 0x2001, Name: AN_NEXT_PAGE_L |
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