ST7LITE49M datasheet(77/188 Pages) STMICROELECTRONICS

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ST7LITE49M

On-chip peripherals

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On-chip peripherals

11.1

Watchdog timer (WDG)

11.1.1

Introduction

The Watchdog timer is used to detect the occurrence of a software fault, usually generated

by external interference or by unforeseen logical conditions, which causes the application

program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on

expiry of a programmed time period, unless the program refreshes the counter’s contents

before the T6 bit becomes cleared.

11.1.2

Main features

●

Programmable free-running downcounter (64 increments of 16000 CPU cycles)

●

Programmable reset

●

Reset (if watchdog activated) when the T6 bit reaches zero

●

Optional reset on HALT instruction (configurable by option byte)

●

Hardware Watchdog selectable by option byte

11.1.3

Functional description

The counter value stored in the CR register (bits T[6:0]), is decremented every 16000

machine cycles, and the length of the timeout period can be programmed by the user in 64

increments.

If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls

over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the RESET

pin for typically 30µs.

Figure 36.

Watchdog block diagram

RESET

WDGA

7-BIT DOWNCOUNTER

fCPU

CLOCK DIVIDER

WATCHDOG CONTROL REGISTER (CR)

÷16000

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