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ST7LITE49M 数据表(PDF) 36 Page - STMicroelectronics |
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ST7LITE49M 数据表(HTML) 36 Page - STMicroelectronics |
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36 / 188 page  Supply, reset and clock management ST7LITE49M 36/188 Figure 12. Clock switching Figure 13. Clock management block diagram Internal RC AWU RC Set RC/AWU Poll AWU_FLAG until set Internal RC Reset RC/AWU Poll RC_FLAG until set AWU RC CR6 CR9 CR2 CR3 CR4 CR5 CR8 CR7 RCCR fOSC MCCSR SMS MCO MCO fCPU fCPU TO CPU AND PERIPHERALS (1ms timebase @ 8 MHz fOSC) /32 DIVIDER fOSC fOSC/32 fOSC fLTIMER 1 0 LITE TIMER 2 COUNTER 8-BIT AT TIMER 2 12-BIT CLKIN OSC2 CLKIN Tunable Oscillator RC /2 DIVIDER Option bits CLKSEL[1:0] OSC 1-16 MHz CLKIN CLKIN /OSC1 OSC /2 DIVIDER OSC/2 CLKIN/2 CLKIN/2 Option bits CLKSEL[1:0] CR1 CR0 SICSR or 32kHz CKCNTCSR RC/AWU Clock controller fCPU AWU RC OSC 8MHz 2MHz 1MHz 4MHz Prescaler 8 MHz (fRC) RC OSC 500kHz CK2 CK1 CK0 AVDTHCR |
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