ST7LITE49M datasheet(17/188 Pages) STMICROELECTRONICS

17 / 188 page

ST7LITE49M

Pin description

17/188

PB0/AIN0

I/O

ei1

Port B0

AIN0

PB1/AIN1/CLKIN

I/O

xxx

Port B1

AIN1/External

clock source

PB2/AIN2

I/O

Port B2

AIN2

PB3/AIN3

I/O

Port B3

AIN3

PB4/AIN4

I/O

Port B4

AIN4

PB5/AIN5

I/O

Port B5

AIN5

PB6/AIN6

I/O

Port B6

AIN6

PB7/AIN7

I/O

Port B7

AIN7

PC0/AIN8

I/O

ei2

Port C0

AIN8

PC1/AIN9

I/O

Port C1

AIN9

PC2/ICCDATA

I/O

Port C2

ICCDATA

PC3/ICCCLK

I/O

Port C3

ICCCLK

PC4/LTIC

I/O

ei2

Port C4

LTIC

PC5

I/O

Port C5

PC6

I/O

ei2

Port C6

PC7/BREAK

I/O

Port C7

BREAK

PA0 (HS)

I/O

ei0

Port A0 (HS)

PA1 (HS)/ATIC

I/O

Port A1 (HS)

ATIC

PA2 (HS)/ATPWM0

I/O

Port A2 (HS)

ATPWM0

In the open-drain output column, T defines a true open-drain I/O (P-Buffer and protection diode to VDD are not

implemented).

It is mandatory to connect all available VDD and VDDA pins to the supply voltage and all VSS and VSSA pins to ground.

Table 2.

Device pin description

number

Pin name

Level

Port/control

Main

function

(after reset)

Alternate

function

Input

Output

ST7LITE49M 数据表(PDF) 17 Page - STMicroelectronics

ST7LITE49M 数据表(HTML) 17 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载