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ST7LITE49M 数据表(PDF) 32 Page - STMicroelectronics

部件名 ST7LITE49M
功能描述  8-bit MCU with single voltage Flash memory data EEPROM, ADC, 8/12-bit timers, and I²C interface
PDF  188 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST7LITE49M 数据表(HTML) 32 Page - STMicroelectronics

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Central processing unit
ST7LITE49M
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6.3.5
Stack Pointer (SP)
Reset value: 01FFh
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the
stack. It is then decremented after data has been pushed onto the stack and incremented
before data is popped from the stack (see Figure 11).
Since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware.
Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer
contains its reset value (the SP6 to SP0 bits are set) which is the stack higher address.
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD
instruction.
Note:
When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit,
without indicating the stack overflow. The previously stored information is then overwritten
and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context
during an interrupt. The user may also directly manipulate the stack by means of the PUSH
and POP instructions. In the case of an interrupt, the PCL is stored at the first location
pointed to by the SP. Then the other registers are stored in the next locations as shown in
Figure 11.
When an interrupt is received, the SP is decremented and the context is pushed on the
stack.
On return from interrupt, the SP is incremented and the context is popped from the
stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
Table 4.
Interrupt software priority truth table
Interrupt software priority
I1
I0
Level 0 (main)
1
0
Level 1
0
1
Level 2
0
0
Level 3 (= interrupt disable)
1
1
15
8
7
0
0
0
0
0
0
0
0
1
1
SP6 SP5 SP4 SP3 SP2 SP1 SP0
Read/write



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