ST7LITE49M datasheet(86/188 Pages) STMICROELECTRONICS

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On-chip peripherals

ST7LITE49M

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When a break function is activated (BA bit =1 and BREN1/BREN2 =1):

●

The break pattern (PWM[3:0] bits in the BREAKCR) is forced directly on the PWMx

output pins if respective OEx is set. (after the inverter).

●

The 12-bit PWM counter CNTR1 is put to its reset value, i.e. 00h (if BREN1 = 1).

●

The 12-bit PWM counter CNTR2 is put to its reset value,i.e. 00h (if BREN2 = 1).

●

ATR1, ATR2, Preload and Active DCRx are put to their reset values.

●

Counters stop counting.

When the break function is deactivated after applying the break (BA bit goes from 1 to 0 by

software), Timer takes the control of PWM ports.

Figure 43.

Block diagram of break function

Output compare mode

To use this function, load a 12-bit value in the Preload DCRxH and DCRxL registers.

When the 12-bit upcounter CNTR1 reaches the value stored in the Active DCRxH and

DCRxL registers, the CMPFx bit in the PWMxCSR register is set and an interrupt request is

generated if the CMPIE bit is set.

In Single Timer mode the output compare function is performed only on CNTR1. The

difference between both the modes is that, in Single Timer mode, CNTR1 can be compared

with any of the four DCR registers, and in Dual Timer mode, CNTR1 is compared with DCR0

or DCR1 and CNTR2 is compared with DCR2 or DCR3.

Note:

The output compare function is only available for DCRx values other than 0 (reset value).

Duty cycle registers are buffered internally. The CPU writes in Preload Duty Cycle registers

and these values are transferred in Active Duty Cycle registers after an overflow event if the

corresponding transfer bit (TRANx bit) is set. Output compare is done by comparing these

active DCRx values with the counters.

PWM0

PWM1

PWM2

PWM3

PWM0

PWM1

PWM2

PWM3

BREAKCR register

BREAK pin

(Inverters)

PWM0

PWM1

PWM2

PWM3

BPEN

Level

Selection

BRSEL

BREDGE BREAKCR register

ENCNTR2 bit

BREN1

BREN2

BREAKEN register

PWM0/1 Break Enable

PWM2/3 Break Enable

OEx

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