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ST7LITE49M 数据表(PDF) 96 Page - STMicroelectronics |
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ST7LITE49M 数据表(HTML) 96 Page - STMicroelectronics |
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96 / 188 page  On-chip peripherals ST7LITE49M 96/188 Bit 0 = CMPIE Compare Interrupt Enable bit This bit is read/write by software and cleared by hardware after a reset. it can be used to mask the interrupt generated when any of the cmpfx bit is set. 0: Output Compare Interrupt Disabled. 1: Output Compare Interrupt Enabled. Counter register 1 High (CNTR1H) Reset value: 0000 0000 (00h) Counter register 1 Low (CNTR1L) Reset value: 0000 0000 (00h) Bits 15:12 = Reserved Bits 11:0 = CNTR1[11:0] Counter value This 12-bit register is read by software and cleared by hardware after a reset. The counter CNTR1 increments continuously as soon as a counter clock is selected. To obtain the 12-bit value, software should read the counter value in two consecutive read operations. As there is no latch, it is recommended to read LSB first. In this case, CNTR1H can be incremented between the two read operations and to have an accurate result when ftimer=fCPU, special care must be taken when CNTR1L values close to FFh are read. When a counter overflow occurs, the counter restarts from the value specified in the ATR1 register. Autoreload register (ATR1H) Reset value: 0000 0000 (00h) 15 8 000 0 CNTR1_ 11 CNTR1_ 10 CNTR1_9 CNTR1_8 Read only 7 0 CNTR1_7 CNTR1_6 CNTR1_5 CNTR1_4 CNTR1_3 CNTR1_2 CNTR1_1 CNTR1_0 Read only 15 8 0 0 0 0 ATR11 ATR10 ATR9 ATR8 Read/write |
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