ST7LITE49M datasheet(39/188 Pages) STMICROELECTRONICS

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ST7LITE49M

Supply, reset and clock management

39/188

7.3

Reset sequence manager (RSM)

7.3.1

Introduction

The reset sequence manager includes three RESET sources as shown in Figure 15:

●

External RESET source pulse

●

Internal LVD RESET (Low Voltage Detection)

●

Internal WATCHDOG RESET

Note:

A reset can also be triggered following the detection of an illegal opcode or prebyte code.

Refer to Section 12.2.1 on page 139 for further details.

These sources act on the RESET pin and it is always kept low during the delay phase.

The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory

mapping.

The basic RESET sequence consists of 3 phases as shown in Figure 14:

●

Active Phase depending on the RESET source

●

256 or 4096 CPU clock cycle delay (see Table 7)

Caution:

When the ST7 is unprogrammed or fully erased, the Flash is blank and the Reset vector is

not programmed. For this reason, it is recommended to keep the RESET pin in low state

until programming mode is entered, in order to avoid unwanted behavior.

The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilize and ensures that

recovery has taken place from the Reset state. The shorter or longer clock cycle delay is

automatically selected depending on the clock source chosen by option byte.

The Reset vector fetch phase duration is 2 clock cycles.

Figure 14.

RESET sequence phases

Table 7.

CPU clock delay during Reset sequence

Clock source

CPU clock

cycle delay

Internal RC 8MHz Oscillator

4096

Internal RC 32kHz Oscillator

256

External clock (connected to CLKIN/PB1 pin)

4096

External Crystal/Ceramic Oscillator

(connected to OSC1/OSC2 pins)

4096

External Crystal/Ceramic 1-16MHz

Oscillator

4096

External Crystal/Ceramic 32kHz

Oscillator

256

RESET

Active Phase

INTERNAL RESET

256 or 4096 CLOCK CYCLES

FETCH

VECTOR

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