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ST7LITE49M 数据表(PDF) 48 Page - STMicroelectronics

部件名 ST7LITE49M
功能描述  8-bit MCU with single voltage Flash memory data EEPROM, ADC, 8/12-bit timers, and I²C interface
PDF  188 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST7LITE49M 数据表(HTML) 48 Page - STMicroelectronics

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Supply, reset and clock management
ST7LITE49M
48/188
Bit 3 = Reserved, must be kept cleared
Bit 2 = LVDRF LVD reset flag
This bit indicates that the last Reset was generated by the LVD block. It is set by
hardware (LVD reset) and cleared by software (by reading). When the LVD is disabled
by option byte, the LVDRF bit value is undefined.
The LVDRF flag is not cleared when another RESET type occurs (external or
watchdog), the LVDRF flag remains set to keep trace of the original failure.
In this case, a watchdog reset can be detected by software while an external reset can
not.
Bit 1 = AVDF Voltage Detector flag
This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt
request is generated when the AVDF bit is set. Refer to Figure 19 and to Section for
additional details.
0: VDD over AVD threshold
1: VDD under AVD threshold
Bit 0 = AVDIE Voltage Detector Interrupt Enable bit
This bit is set and cleared by software. It enables an interrupt to be generated when the
AVDF flag is set. The pending interrupt information is automatically cleared when
software enters the AVD interrupt routine.
0: AVD interrupt disabled
1: AVD interrupt enabled
Table 11.
Reset source selection
RESET source
LVDRF
WDGRF
External RESET pin
0
0
Watchdog
0
1
LVD
1
X
Table 12.
Clock register mapping and reset values
Address
(Hex.)
Register
label
76
5
4
3
2
1
0
003Ah
MCCSR
Reset
Value
-
0
-
0
-
0
-
0
-
0
-
0
MCO
0
SMS
0
003Bh
RCCR
Reset
Value
CR9
1
CR8
1
CR7
1
CR6
1
CR5
1
CR4
1
CR3
1
CR2
1
003Ch
SICSR
Reset
Value
-
0
CR1
1
CR0
1
WDGRF
0
-
0
LVDRF
x
AVDF
x
AVDIE
0



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