ST7LITE49M datasheet(98/188 Pages) STMICROELECTRONICS

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On-chip peripherals

ST7LITE49M

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Bit 1 = OPx PWMx Output Polarity bit

This bit is read/write by software and cleared by hardware after a reset. This bit selects

the polarity of the PWM signal.

0: The PWM signal is not inverted.

1: The PWM signal is inverted.

Bit 0 = CMPFx PWMx Compare flag

This bit is set by hardware and cleared by software by reading the PWMxCSR register.

It indicates that the upcounter value matches the Active DCRx register value.

0: Upcounter value does not match DCRx value.

1: Upcounter value matches DCRx value.

Break Control register (BREAKCR)

Reset value: 0000 0000 (00h)

Bit 7 = Reserved.

Bit 6 = BREDGE Break Input Edge Selection bit

This bit is read/write by software and cleared by hardware after reset. It selects the

active level of Break signal.

0: Low level of Break selected as active level

1: High level of Break selected as active level

Bit 5 = BA Break Active bit

This bit is read/write by software, cleared by hardware after reset and set by hardware

when the active level defined by the BREDGE bit is applied on the BREAK pin. It

activates/deactivates the Break function.

0: Break not active

1: Break active

Bit 4 = BPEN Break Pin Enable bit

This bit is read/write by software and cleared by hardware after Reset.

0: Break pin disabled

1: Break pin enabled

Bits 3:0 = PWM[3:0] Break Pattern bits

These bits are read/write by software and cleared by hardware after a reset. They are

used to force the four PWMx output signals into a stable state when the Break function

is active and corresponding OEx bit is set.

BREDGE

BPEN

PWM3

PWM2

PWM1

PWM0

Read/write

ST7LITE49M 数据表(PDF) 98 Page - STMicroelectronics

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