ST7LITE49M datasheet(102/188 Pages) STMICROELECTRONICS

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On-chip peripherals

ST7LITE49M

102/188

Bit 1= TRAN2 Transfer enable2 bit

This bit is read/write by software, cleared by hardware after each completed transfer

and set by hardware after reset. It controls the transfers on CNTR2.

It allows the value of the Preload DCRx registers to be transferred to the Active DCRx

registers after the next overflow event.

The OPx bits are transferred to the shadow OPx bits in the same way.

Note:

DCR2/3 transfer will be controlled using this bit if ENCNTR2 bit is set.

This bit must not be reset by software

Bit 0 = TRAN1 Transfer enable 1 bit

This bit is read/write by software, cleared by hardware after each completed transfer

and set by hardware after reset. It controls the transfers on CNTR1. It allows the value

of the Preload DCRx registers to be transferred to the Active DCRx registers after the

next overflow event.

The OPx bits are transferred to the shadow OPx bits in the same way.

Note:

DCR0,1 transfers are always controlled using this bit.

DCR2/3 transfer will be controlled using this bit if ENCNTR2 is reset.

This bit must not be reset by software

Autoreload register 2 (ATR2H)

Reset value: 0000 0000 (00h)

Autoreload register (ATR2L)

Reset value: 0000 0000 (00h)

Bits 11:0 = ATR2[11:0] Autoreload register 2

This is a 12-bit register which is written by software. The ATR2 register value is

automatically loaded into the upcounter CNTR2 when an overflow of CNTR2 occurs. The

0000

ATR11

ATR10

ATR9

ATR8

Read/write

ATR7

ATR6

ATR5

ATR4

ATR3

ATR2

ATR1

ATR0

Read/write

ST7LITE49M 数据表(PDF) 102 Page - STMicroelectronics

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