ST7LITE49M datasheet(145/188 Pages) STMICROELECTRONICS

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ST7LITE49M

Electrical characteristics

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13.3

Operating conditions

13.3.1

General operating conditions

TA = -40 to +125 °C unless otherwise specified.

Figure 62.

fCPU maximum operating frequency versus VDD supply voltage

13.3.2

Operating conditions with Low Voltage Detector (LVD)

TA = -40 to 125 °C unless otherwise specified.

Table 68.

General operating conditions

Symbol

Parameter

Conditions

Min

Max

Unit

VDD

Supply voltage

fCPU = 4 MHz. max.

2.4

5.5

fCPU = 8 MHz. max.

3.3

5.5

fCPU

CPU clock frequency

3.3 V

≤ V

DD≤5.5 V

up to 8

MHz

2.4 V

≤V

DD<3.3 V

up to 4

fCPU [MHz]

SUPPLY VOLTAGE [V]

2.0

2.4

3.3

3.5

4.0

4.5

5.0

FUNCTIONALITY

NOT GUARANTEED

IN THIS AREA

5.5

FUNCTIONALITY

GUARANTEED

IN THIS AREA

(UNLESS OTHERWISE

STATED IN THE

TABLES OF

PARAMETRIC DATA)

2.7

Table 69.

Operating characteristics with LVD

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIT+(LVD)

Reset release threshold

(VDD rise)

High Threshold

Med. Threshold

Low Threshold

3.9

3.2

2.5

4.2

3.5

2.7

4.5

3.8

3.0

VIT-(LVD)

Reset generation threshold

(VDD fall)

High Threshold

Med. Threshold

Low Threshold

3.7

3.0

2.4

4.0

3.3

2.6

4.3

3.6

2.9

Vhys

LVD voltage threshold hysteresis

VIT+(LVD)-VIT-(LVD)

150

VtPOR

VDD rise time rate

(1)(2)

Not tested in production. The VDD rise time rate condition is needed to ensure a correct device power-on

and LVD reset release. When the VDD slope is outside these values, the LVD may not release properly the

reset of the MCU.

Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the

application, it is recommended to pull VDD down to 0V to ensure optimum restart conditions. Refer to circuit

example in Figure 96 on page 171.

µs/V

IDD(LVD)

LVD/AVD current consumption

VDD = 5 V

140

µA

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