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TMP93CS41 数据表(PDF) 34 Page - Toshiba Semiconductor |
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TMP93CS41 数据表(HTML) 34 Page - Toshiba Semiconductor |
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34 / 248 page ![]() TMP93CS40/TMP93CS41 2004-02-10 93CS40-32 Table 3.3.8 Pin States in STOP Mode TMP93CS40 TMP93CS41 Pin name I/O <DRVE> = 0 <DRVE> = 1 <DRVE> = 0 <DRVE> = 1 P00 to P07 Input mode Output mode AD8 to AD15 ▲ − − ▲ Output − × × − × × − P10 to P17 Input mode Output mode AD0 to AD7 ▲ − − ▲ Output − × × − × × − P20 to P27 Input mode Output mode, A0 to A7/A16 to A23 ▲ ▲ ▲ Output ▲ ▲ ▲ Output P30 ( RD ), P31 ( WR ) Output − Output − “H” P32 to P37 Input mode Output mode PU* PU* Input Output P40, P41 Input mode Output mode PU* PU* Input Output P42 (CS2/CAS2) Input mode Output mode PD* PD* Input Output P5 Input mode ▲ ▲ P6 Input mode Output mode PU* PU* Input Output P7 Input mode Output mode PU* PU* Input Output P80 to P86 Input mode Output mode PU* PU* Input Output P87 (INT0) Input mode Output mode Input mode (INT0) PU PU Input Input Output Input P90 to P95 Input mode Output mode PU* PU* Input Output PA0 to PA6 Input mode Output mode − − Input Output PA7 Input mode Output mode, SCOUT − − Input Output NMI Input Input Input WDOUT Output Output Output ALE Output (<ALEEN> = 1) “L” “L” CLK Output (<CLKEN> = 1) − “H” RESET Input Input Input EA Input Input Input AM8/ AM16 Input Input Input X1 Input − − X2 Output “H” “H” P96 Input mode Output mode XT1 − − − Input Output* − − − P97 Input mode Output mode XT2 − Input Output* − The same as for TMP93CS40 (Align) −: Input is not accepted; output is at high impedance. Input: Input gate in operation. Fix input voltage to “L” or “H” so that the input state pin stays constant. Output: Output state. Output*: Open-drain output state. Input gate in operation. Set output to “L” or attach pull up on pin so that the input gate stays constant. PU: Programmable pull-up pin. When a pull-up resistor is not set, fix the pin to avoid through current because the input gate always operates. PU*: Programmable pull-up pin in input gate disable state. No through current flows even if the pin is set to high impedance. PD*: Programmable pull-down pin in input gate disable state. No through current flows even if the pin is set to high impedance. ▲: When a HALT instruction is executed and CPU stops at the address of the port register, an input gate operates. Fix the pin to avoid through current, and change the program. In all other cases, input is not accepted; output is at high impedance. ×: Cannot be set. |
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