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TMP93CS41 数据表(PDF) 31 Page - Toshiba Semiconductor |
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TMP93CS41 数据表(HTML) 31 Page - Toshiba Semiconductor |
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31 / 248 page  TMP93CS40/TMP93CS41 2004-02-10 93CS40-29 3. IDLE1 mode In the IDLE1 mode, only the internal oscillator operates. The system clock in the MCU stops, and the CLK pin is fixed at the level H in the output enabled state. (CKOCR<CLKEN> = 1) In the halt state, an interrupt request is sampled unsyncronously with the system clock, however the halt release (Restart of operation) is performed synchronously with it. IDLE1 mode is released by external interrupts (NMI, INT0). (See Table 3.3.6 “Halt Release Sources and Halt Release Operations”.) When the IDLE mode is used, set (TRUN<PRRUN> to 0) to stop the 9 bit and 5 bit prescaler before a HALT instruction is executed, to reduce the power consumption. Figure 3.3.7 illustrates the timing for releasing the halt state by interrupts in the IDLE1 mode Figure 3.3.7 Timing Chart of Halt State Release by Interrupts in IDLE1 Mode Address Address + 2 Address Data Address Data X1 CLK A0 to A23 ALE AD0 to AD15 RD WR NMI INT0 (Level) INT0 (Rising edge) IDLE1 mode |
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