TMP93CS41 datasheet(11/248 Pages) TOSHIBA

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TMP93CS40/TMP93CS41

2004-02-10

93CS40-9

Operation

This section describes in blocks the functions and basic operations of TMP93CS40 and

TMP93CS41 devices. Please also refer to section 7. Precautions in use, which describes some

points requiring careful attention.

3.1

CPU

TMP93CS40 and TMP93CS41 devices have a built-in high-performance 16-bit CPU (900/L

CPU). (For basics of the CPU operation, see the information on the TLCS-900/L CPU in the

previous chapter.)

This section describes some CPU functions unique to the TMP93CS40 and TMP93CS41, that

are not described in the previous chapter, entitled TLCS-900/L CPU.

3.1.1

Reset

When resetting the TMP93CS40 and TMP93CS41 microcontroller, ensure that the power

supply voltage is within the operating voltage range, and that the internal high-frequency

oscillator has stabilized. Then set the RESET input to low level at least for 10 system

clocks (16

µs at 20 MHz). Thus, when turn on the switch, be set to the power supply voltage

is within the operating voltage range, and that the internal high-frequency oscillator has

stabilized. Then hold the RESET input to low level at least for 10 system clocks.

Clock gear is initialized 1/16 mode by reset operation. It means that the system clock

mode fSYS is set to fc/32 (= fc/16 × 1/2).

When a reset signal is accepted, the CPU sets itself as follows:

•

The program counter (PC) is set according to the reset vector that is stored from 8000H

to 8002H.

PC<7:0>

← Data in location 8000H

PC<15:8>

← Data in location 8001H

PC<23:16>

← Data in location 8002H

•

The stack pointer (XSP) for system mode is set to 100H.

•

The <IFF2:0> bits of the status register SR are set to 111. (Sets mask register to

interrupt level 7.)

•

The <MAX> bit of SR is set to 1. (Sets to maximum mode. See previous chapter.)

•

The <RFP2:0> bits of SR are set to 000. (Clears register banks to 0.)

When the reset is released, instruction execution starts from PC (The reset vector). The

reset makes no changes in any CPU internal registers other than those specifically

mentioned above.

When a reset is received, signal and data processing for built-in I/Os, ports, and other

pins is affected as follows:

•

Initializes built-in I/O registers as per specifications.

•

Sets port pins (including pins also used as built-in I/Os) to general-purpose

input/output port mode.

•

Sets the WDTOUT pin to 0. (The watchdog timer is set to enable after reset.)

•

Pulls up the CLK pin to 1.

•

Sets the ALE pin to 0 in the case of the TMP93CS41, and to high impedance (High-Z) in

the case of TMP93CS40.

Note 1: Resetting makes no change in any register in the CPU except the program counter (PC),

status register (SR) and stack pointer (XSP), nor in the data in the internal RAM.

Note 2: The CLK pin is pulled up during reset. When the voltage is externally reduced, there is a

possibility of causing malfunctions.

Figure 3.1.1 and Figure 3.1.2 show the reset timing chart of the TMP93CS41 and

TMP93CS40.

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