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TMP93CS41 数据表(PDF) 68 Page - Toshiba Semiconductor |
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TMP93CS41 数据表(HTML) 68 Page - Toshiba Semiconductor |
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68 / 248 page ![]() TMP93CS40/TMP93CS41 2004-02-10 93CS40-66 Port 3 Register 7 6 5 4 3 2 1 0 P3 Bit symbol P37 P36 P35 P34 P33 P32 P31 P30 (0007H) Read/Write R/W After reset 1 1 1 1 1 1 1 1 Function Input mode (Pull up) Output mode Port 3 Control Register 7 6 5 4 3 2 1 0 P3CR Bit symbol P37C P36C P35C P34C P33C P32C (000AH) Read/Write W After reset 0 0 0 0 0 0 Function 0: Input 1: Output Port 3 Function Register 7 6 5 4 3 2 1 0 P3FC Bit symbol P37F P36F P35F P34F P32F P31F P30F (000BH) Read/Write W W After reset 0 0 0 0 0 0 0 Function 0: Port 1: RAS 0: Port 1: R/ W 0: Port 1: BUSAK 0: Port 1: BUSRQ 0: Port 1: HWR 0: Port 1: WR 0: Port 1: RD Figure 3.5.9 Registers for Port 3 I/O setting 0 Input 1 Output R/ W setting P3FC<P36F> 1 P3CR<P36C> 1 RAS setting P3FC<P37F> 1 P3CR<P37C> 1 Note 1: Read-modify-write is prohibited for registers P3CR and P3FC. Note 2: When port P3 is used in the input mode, the P3 register controls the built-in pull-up resistor. Read-modify-write is prohibited in the input mode or the I/O mode, as it may affect the states of the pull-up/pull-down resistors. Note 3: When the P33/WAIT pin is used as a WAIT pin, set P3CR<P33C> to “0” and set the chip select/WAIT control register <BnW1:0> to “10”. BUSRQ setting P3FC<P34F> 1 P3CR<P34C> 0 BUSAK setting P3FC<P35F> 1 P3CR<P35C> 1 <P30> <P30F> 0 1 0 “0” output “1” output 1 Always RD output (for pseudo SRAM) RD output only for external access P30 ( RD ) function setting <P31> <P31F> 0 1 0 “0” output “1” output 1 WR output only for external access P31 ( WR ) function setting HWR setting P3FC<P32F> 1 P3CR<P32C> 1 |
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