TMP93CS41 datasheet(7/248 Pages) TOSHIBA

7 / 248 page

TMP93CS40/TMP93CS41

2004-02-10

93CS40-5

2.2

Pin Names and Functions

The names of the input/output pins and their functions are described below.

Table 2.2.1 to Table 2.2.4 show pin names and functions.

Table 2.2.1 Pin Names and Functions (1/4)

Pin Names

Number

of Pins

I/O

Functions

P00 to P07

AD0 to AD7

I/O

Tri-state

Port 0: I/O port that allows at the bit level

Address/data (lower): Bits 0 to 7 of address/data bus

P10 to P17

AD8 to AD15

A8 to A15

I/O

Tri-state

Output

Port 1: I/O port that allows at the bit level

Address data (upper): Bits 8 to 15 of address/data bus

Address: Bits 8 to 15 of address bus

P20 to P27

A0 to A7

A16 to A23

I/O

Output

Port 2: I/O port that allows selection of I/O at the bit level

(with pull-down resistor)

Address: bits 0 to 7 of address bus

Address: bits 16 to 23 of address bus

P30

Output

Port 30: Output port

Read: Strobe signal for reading external memory

P31

Output

Port 31: Output port

Write: Strobe signal for writing data on pins AD0 to AD7

P32

HWR

I/O

Output

Port 32: I/O port (with pull-up resistor)

High write: Strobe signal for writing data on pins AD8 to AD15

P33

WAIT

I/O

Input

Port 33: I/O port (with pull-up resistor)

Wait: in used to request CPU bus wait

P34

BUSRQ

I/O

Input

Port 34: I/O port (with pull-up resistor)

Bus request: Signal used to request bus release

P35

BUSAK

I/O

Output

Port 35: I/O port (with pull-up resistor)

Bus acknowledge: Signal used to acknowledge bus release

P36

I/O

Output

Port 36: I/O port (with pull-up resistor)

Read/write: 1 represents read or dummy cycle; 0 represents write cycle.

P37

RAS

I/O

Output

Port 37: I/O port (with pull-up resistor)

Row address strobe: Outputs RAS strobe for DRAM.

P40

CS0

CAS

I/O

Output

Port 40: I/O port (with pull-up resistor)

Chip select 0: Outputs 0 when address is within specified address area.

Column address strobe 0: Outputs CAS strobe for DRAM when address is within

specified address area.

Note: This device’s built-in memory or built-in I/O cannot be accessed by an external DMA controller using

the BUSRQ and BUSAK signals.

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