TMP93CS41 datasheet(29/248 Pages) TOSHIBA

29 / 248 page

TMP93CS40/TMP93CS41

2004-02-10

93CS40-27

When releasing the HALT mode by resetting, the internal RAM data keeps the state

before the “HALT” instruction is executed. However the other setting contents are

initialized (Releasing due to interrupts keep the state before the “HALT” instruction is

executed.)

When the HALT mode is released by resetting, the internal RAM data maintains the

state it was in before the HALT instruction was executed.

However the other setting contents are initialized. (Release of the HALT mode due to

interrupts maintains all setting contents in their states before the HALT instruction

was executed.)

Table 3.3.6 Halt Release Sources and Halt Release Operations

Interrupt Enabled

Interrupt Disabled

Interrupt Receiving Status

(Interrupt level) ≥ (Interrupt mask)

(Interrupt level) < (Interrupt mask)

HALT Mode

RUN

IDLE2 IDLE1 STOP

RUN

IDLE2 IDLE1 STOP

NMI

♦

−

INTWDT

♦

−

INT0

♦

○

INT4 to INT7

♦

INTT0 to INTT3

♦

INTTR4 to INTTR7

♦

INTRX0, TX0

♦

INTRX1, TX1

♦

Interrupt

INTAD

♦

Halt release

source

RESET

♦

♦: After release of the HALT mode, the CPU starts interrupt processing. (RESET initializes LSI.)

○: After release of the HALT mode, the CPU starts executing the next instruction that follows the HALT instruction.

×: Cannot be used to release the HALT mode.

−: This combination type does not exist because the priority level (Interrupt request level) of non-maskable interrupts is fixed to the

highest priority level 7.

*1: Release the HALT mode is executed after the warm-up cycle is completed.

Note: When release of the HALT mode is executed by an INT0 interrupt of the level mode in the interrupt enabled status, maintain

level H until the start of interrupt processing. If level L is set before the start of interrupt processing, interrupt processing is

correctly started.

Example of releasing the RUN mode:

An INT0 interrupt releases the halt state when the RUN mode is on.

Address

8203H

(IIMC), 00H

; Select interrupt rising edge.

8206H

(INTE0AD), 06H

; Sets interrupt level to 6 for INT0.

8209H

; Sets interrupt level to 5 for CPU.

820BH

(WDMOD), 00H

; Sets HALT mode to run.

820EH

HALT

; Halts CPU.

820FH

XX, XX

RETI

INT0 interrupt routine

INT0

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