TMP93CS41 datasheet(30/248 Pages) TOSHIBA

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TMP93CS40/TMP93CS41

2004-02-10

93CS40-28

(3) Operation

1. RUN mode

In the RUN mode, the system clock in the MCU continues to operate even after a

HALT instruction is executed. Only the CPU stops executing further instructions.

In the halt state, an interrupt request is accepted on the falling edge of the CLK

signal.

Release of the RUN mode is executed by the external or internal interrupts. (See

Table 3.3.6 “Halt Release Sources and Halt Release Operations”.)

Figure 3.3.6 shows the timing for releasing the halt state by interrupts in the RUN

or IDLE2 modes.

Figure 3.3.6 Timing Chart for Releasing the Halt State by Interrupt in RUN/IDLE2 Modes

2. IDLE2 mode

In the IDLE2 mode, the system clock signal is supplied only to specific internal I/O

devices, and the CPU stops executing the current instruction. In the IDLE2 mode, the

halt state is released by an interrupt with the same timing as in the RUN mode. The

IDLE2 mode is released by external or internal interrupts, except for INTWDT and

INTAD interrupts. (See Table 3.3.6 “Halt Release Sources and Halt Release

Operations”.)

In the IDLE2 mode, the watchdog timer should be disabled before entering the halt

status, to prevent the watchdog timer interrupt from occurring just after release of the

HALT mode.

Address

+ 2

Address

Data

Address

Data

CLK

A0 to A23

ALE

AD0 to AD15

NMI

INT0

(

Level)

INT4 to INT7

(Rising edge)

INT4, INT6

(Falling edge)

Internal INT

RUN or IDLE2

modes

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