TMP93CS41 datasheet(43/248 Pages) TOSHIBA

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TMP93CS40/TMP93CS41

2004-02-10

93CS40-41

3.4.2

Micro DMA

In addition to the conventional interrupt processing, the TMP93CS40 and TMP93CS41

also have a micro DMA function. When an interrupt is accepted, in addition to an interrupt

vector, the CPU receives data indicating whether it is to be processed in micro DMA mode

or in general-purpose interrupt mode. The CPU performs micro DMA processing only if

that mode is requested.

The micro DMA of the TMP93CS40 and TMP93CS41 can process at very high speed

compared with the TLCS-90 micro DMA because it has transfer parameters in dedicated

registers in the CPU. Since those dedicated registers are assigned as CPU control registers,

they can only be accessed by the LDC instruction.

(1) Micro DMA operation

Micro DMA operation starts when the accepted interrupt vector value matches the

micro DMA start vector value set in the interrupt controller. The micro DMA has four

channels, so that it can be set for up to four types of interrupt sources at the same time.

When a micro DMA interrupt is accepted, data are automatically transferred from

the transfer source address to the transfer destination address set in the control

decrementing is other than “0”, micro DMA processing is completed; if the value in the

counter after decrementing is “0”, general-purpose interrupt processing is performed.

In read-only mode, which provides for DRAM refresh, the value in the counter is

ignored and a dummy read operation is repeated.

32-bit control registers are used for setting transfer source and destination

addresses. However, the TMP93CS40 and TMP93CS41 have only 24 address pins for

output. A 16-Mbyte space is available for the micro DMA.

There are two data transfer modes: One-byte mode and one-word mode.

Incrementing, decrementing, and fixing the transfer source and destination addresses

after transfer can be done in both modes. Therefore data can easily be transferred

between I/O and memory and between different I/Os. For details of transfer modes, see

the description of transfer mode registers.

The transfer counter has 16 bits, so up to 65536 transfers (The maximum when the

initial value of the transfer counter is 0000H) can be performed for one interrupt

source by micro DMA processing.

When the transfer counter is decremented to “0” after data are transferred by the

micro DMA, general-purpose interrupt processing is performed. After processing the

general-purpose interrupt, restarting the interrupts of the same channel restarts the

transfer counter from 65536. It is necessary to reset the transfer counter in the

general-purpose interrupt processing routine.

Interrupt sources handled by micro DMA processing are 20 in total, and the micro

DMA start vectors are listed in Table 3.4.1.

The following timing chart is a micro DMA cycle of the transfer address increment

(INC) mode (The other modes are the same as this except for the read-only mode).

(Conditions: MAX mode, 16-bit bus width for 16 Mbytes, 0 waits.)

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