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TMP93CS41 数据表(PDF) 93 Page - Toshiba Semiconductor |
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TMP93CS41 数据表(HTML) 93 Page - Toshiba Semiconductor |
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93 / 248 page  TMP93CS40/TMP93CS41 20004-02-10 93CS40-91 Table 3.6.2 Dynamic Bus Sizing CPU Data Operand Data Size Operand Start Address Memory Data Size CPU Address D15 to D8 D7 to D0 8 bits 2n + 0 8 bits 2n + 0 xxxxx b7 to b0 (Even number) 16 bits 2n + 0 xxxxx b7 to b0 2n + 1 8 bits 2n + 1 xxxxx b7 to b0 (Odd number) 16 bits 2n + 1 b7 to b0 xxxxx 16 bits 2n + 0 (Even number) 8 bits 2n + 0 2n + 1 xxxxx xxxxx b7 to b0 b15 to b8 16 bits 2n + 0 b15 to b8 b7 to b0 2n + 1 (Odd number) 8 bits 2n + 1 2n + 2 xxxxx xxxxx b7 to b0 b15 to b8 16 bits 2n + 1 2n + 2 b7 to b0 xxxxx xxxxx b15 to b8 32 bits 2n + 0 (Even number) 8 bits 2n + 0 2n + 1 2n + 2 2n + 3 xxxxx xxxxx xxxxx xxxxx b7 to b0 b15 to b8 b23 to b16 b31 to b24 16 bits 2n + 0 2n + 2 b15 to b8 b31 to b24 b7 to b0 b23 to b16 2n + 1 (Odd number) 8 bits 2n + 1 2n + 2 2n + 3 2n + 4 xxxxx xxxxx xxxxx xxxxx b7 to b0 b15 to b8 b23 to b16 b31 to b24 16 bits 2n + 1 2n + 2 2n + 4 b7 to b0 b23 to b16 xxxxx xxxxx b15 to b8 b31 to b24 xxxxx: During a read, data input to the bus is ignored. While writing, the bus is at high impedance and the write strobe signal remains in active. |
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