TMP93CS41 datasheet(65/248 Pages) TOSHIBA

65 / 248 page

TMP93CS40/TMP93CS41

2004-02-10

93CS40-63

3.5.4

Port 3 (P30 to P37)

Port 3 is an 8-bit general-purpose I/O port.

I/O can be set on a bit basis, but note that P30 and P31 are used for output only. I/O is set

using control register P3CR and function register P3FC. Resetting sets all bits of output

latch P3 to P1, and control register P3CR (bits 0 and 1 are unused) and function register

P3FC to 0. Resetting also outputs 1 from P30 and P31, sets P32 to P37 to input mode, and

connects a pull-up resistor.

In addition to functioning as a general-purpose I/O port, port 3 also functions as an I/O

for the CPU’s control/status signal.

When the P30 pin is defined as RD signal output mode (<P30F>

= 1), in the TMP93CS40

or the TMP93CS41 is used, clearing the output latch register <P30> to 0 outputs the RD

strobe (used for the pseudo-static RAM) from the P30 pin even when the internal address

area is accessed.

If the output latch register <P30> remains 1, the RD strobe signal is output only when

the external address area is accessed.

In the TMP93CS41, which needs external ROMs, P30 outputs the RD signal and P31

outputs the WR signal, regardless of the values set in function registers P30F and P31F.

TMP93CS41 数据表(PDF) 65 Page - Toshiba Semiconductor