TMP93CS41 datasheet(32/248 Pages) TOSHIBA

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TMP93CS40/TMP93CS41

2004-02-10

93CS40-30

4. STOP mode

The STOP mode is selected to stop all internal circuits including the internal

oscillator.

The pin status in the STOP mode depends on the setting of a bit in the watchdog

timer mode register WDMOD<DRVE>. (See Table 3.3.8 for setting of

WDMOD<DRVE>.) Table 3.3.8 summarizes the state of these pins in the STOP mode.

The STOP mode is released by external interrupts (NMI, INT0). When the STOP

mode is released, the system clock output starts after the warm-up time required to

attain stable oscillation.

The warm-up time can be set using WDMOD<WARM>. See the example of warm-up

time setting (Table 3.3.7).

In a system which supplies a stable clock signal generated by an external oscillator,

the warm-up time can be reduced by using the setting of T45CR<QCU>.

Figure 3.3.8 illustrates the timing for releasing the halt state by interrupts during

the STOP mode.

Figure 3.3.8 Timing Chart of Halt State Release by Interrupts in STOP Mode

Table 3.3.7 Example of Warm-up Time after Releasing the STOP Mode

Warm-up Time [ms]

Clock Operation

Frequency after the

STOP Mode is

Released

WDMOD<WARM>

= 0WDMOD<WARM> = 1

Clock

Frequency

0.8192

3.2768

fc/2

1.6384

6.5536

fc/4

3.2768

13.1072

fc/8

6.5536

26.2144

fc/16

13.1072

52.4288

= 20 MHz

500

2000

= 32.768 kHz

Address

+ 2

Address

Data

Address

Data

CLK

A0 to A23

ALE

AD0 to AD15

INT0

(Level)

INT0

(Rising edge)

STOP

mode

Warm-up

time

NMI

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