TMP93CS41 datasheet(111/248 Pages) TOSHIBA

111 / 248 page

TMP93CS40/TMP93CS41

20004-02-10

93CS40-109

In this mode, a programmable square wave is generated by inverting the timer output

each time the 8-bit up counter (UC0) matches the timer registers TREG0 and TREG1.

However, it is necessary for the set value of TREG0 to be smaller than that of TREG1.

Though the up counter (UC1) of timer 1 is not used in this mode, UC1 should be set for

counting by setting TRUN<T1RUN> to “1”.

Figure 3.7.11 shows the block diagram for this mode.

Figure 3.7.11 Block Diagram of 8-Bit PPG Output Mode

When the double buffer of TREG0 is enabled in this mode, the value of the register buffer

will be shifted in TREG0 each time TREG1 matches UC0.

Use of the double buffer makes the handling of low duty waves easy (when duty is

varied).

Figure 3.7.12 Operation of Register Buffer

Match with TREG0

and up counter 0

Match with TREG1

TREG0

(Value to be compared)

(Up counter

= Q1)

TREG 0 (Register buffer)

write

(Up counter

= Q2)

Shift from register buffer

TI0 pin

φT1

φT4

φT16

TMOD<T0CLK1:0>

Selector

TRUN<T0RUN>

TREG0-WR

8-bit

up counter (UC0)

TFF1

Inversion

TO1

TFFCR

<TFF1C1:0, TFF1IE>

Selector

Shift trigger

TFFCR<DBEN>

Comparator

TREG0

Comparator

TREG1

INTT1

Internal data bus

INTT0

TMP93CS41 数据表(PDF) 111 Page - Toshiba Semiconductor

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