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TMP93CS41 数据表(PDF) 217 Page - Toshiba Semiconductor |
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TMP93CS41 数据表(HTML) 217 Page - Toshiba Semiconductor |
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217 / 248 page  TMP93CS40/TMP93CS41 2004-02-10 93CS40-215 4.4 AD Conversion Characteristics AVCC = VCC, AVSS = VSS Parameter Symbol Power Supply Min Typ Max Unit VCC = 5 V ± 10% VCC − 1.5 V VCC VCC Analog reference voltage ( +) VREFH VCC = 3 V ± 10% VCC − 0.2 V VCC VCC VCC = 5 V ± 10% VSS VSS VSS + 0.2 V Analog reference voltage ( −) VREFL VCC = 3 V ± 10% VSS VSS VSS + 0.2 V Analog input voltage range VAIN VREFL VREFH V VCC = 5 V ± 10% 0.5 1.5 Analog current for analog reference voltage <VREFON> = 1 VCC = 3 V ± 10% 0.3 0.9 mA <VREFON> = 0 IREF (VREFL = 0 V) VCC = 2.7 to 5.5 V 0.02 5.0 µA VCC = 5 V ± 10% ±1.0 ±3.0 Error (not including quantizing errors) − VCC = 3 V ± 10% ±1.0 ±3.0 LSB Note 1: 1LSB = (VREFH − VREFL)/210 [V] Note 2: The operation of this AD converter is guaranteed only using fc (The high-frequency oscillator). It is not guaranteed for fs. The operation above is guaranteed for fFPH ≥ 4 MHz. Note 3: The value ICC includes the current which flows through the AVCC pin. 4.5 Serial Channel Timing (1) I/O interface mode 1. SCLK input mode Variable 32.768 MHz (Note) 12.5 MHz 20 MHz Parameter Symbol Min Max Min Max Min Max Min Max Unit SCLK cycle tSCY 16X 488 1.28 0.8 µs Output data → Rising edge or falling edge* of SCLK tOSS tSCY/2 − 5X − 50 91.5 µs 190 100 ns SCLK rising edge or falling edge* → Output data hold tOHS 5X − 100 152 µs 300 150 ns SCLK rising edge or falling edge* → Input data hold tHSR 0 0 0 0 ns SCLK rising edge or falling edge* → Effective data input tSRD tSCY − 5X − 100 336 µs 780 450 ns Note: System clock is fs, or input clock to prescaler is divisor clock of fs. * The rising edge is used in SCLK rising mode. The falling edge is used SCLK falling mode. 2. SCLK output mode Variable 32.768 MHz (Note) 12.5 MHz 20 MHz Parameter Symbol Min Max Min Max Min Max Min Max Unit SCLK cycle (Programmable) tSCY 16X 8192X 488 250 ms 1.28 655.36 0.8 409.6 µs Output data → SCLK rising edge tOSS tSCY − 2X − 150 427 µs 970 550 ns SCLK rising edge → Output data hold tOHS 2X − 80 60 µs 80 20 ns SCLK rising edge → Input data hold tHSR 0 0 0 0 ns SCLK rising edge → Effective data input tSRD tSCY − 2X − 150 428 µs 970 550 ns Note: System clock is fs, or input clock to prescaler is divisor clock of fs. |
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