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ST10F271 数据表(PDF) 133 Page - STMicroelectronics |
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ST10F271 数据表(HTML) 133 Page - STMicroelectronics |
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133 / 173 page  ST10F271 Electrical characteristics 133/173 negative injection current). 8. Refer to scheme reported in Figure 40: A/D converter input pins scheme. 24.7.1 Conversion timing control When a conversion is started, first the capacitances of the converter are loaded via the respective analog input pin to the current analog input voltage. The time to load the capacitances is referred to as sample time. Next the sampled voltage is converted to a digital value several successive steps, which correspond to the 10-bit resolution of the ADC. During these steps the internal capacitances are repeatedly charged and discharged via the VAREF pin. The current that has to be drawn from the sources for sampling and changing charges depends on the time that each respective step takes, because the capacitors must reach their final voltage level within the given time, at least with a certain approximation. The maximum current, however, that a source can deliver, depends on its internal resistance. The time that the two different actions during conversion take (sampling, and converting) can be programmed within a certain range in the ST10F271 relative to the CPU clock. The absolute time that is consumed by the different conversion steps therefore is independent from the general speed of the controller. This allows adjusting the A/D converter of the ST10F271 to the properties of the system: Fast conversion can be achieved by programming the respective times to their absolute possible minimum. This is preferable for scanning high frequency signals. The internal resistance of analog source and analog supply must be sufficiently low, however. High internal resistance can be achieved by programming the respective times to a higher value, or the possible maximum. This is preferable when using analog sources and supply with a high internal resistance in order to keep the current as low as possible. The conversion rate in this case may be considerably lower, however. The conversion times are programmed via the upper four bits of register ADCON. Bit fields ADCTC and ADSTC are used to define the basic conversion time and in particular the partition between sample phase and comparison phases. The table below lists the possible combinations. The timings refer to the unit TCL, where fCPU = 1/2TCL. A complete conversion time includes the conversion itself, the sample time and the time required to transfer the digital value to the result register. Table 67. A/D converter programming ADCTC ADSTC Sample Comparison Extra Total conversion 00 00 TCL * 120 TCL * 240 TCL * 28 TCL * 388 00 01 TCL * 140 TCL * 280 TCL * 16 TCL * 436 00 10 TCL * 200 TCL * 280 TCL * 52 TCL * 532 00 11 TCL * 400 TCL * 280 TCL * 44 TCL * 724 11 00 TCL * 240 TCL * 480 TCL * 52 TCL * 772 11 01 TCL * 280 TCL * 560 TCL * 28 TCL * 868 11 10 TCL * 400 TCL * 560 TCL * 100 TCL * 1060 11 11 TCL * 800 TCL * 560 TCL * 52 TCL * 1444 10 00 TCL * 480 TCL * 960 TCL * 100 TCL * 1540 |
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