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ST10F271 数据表(PDF) 132 Page - STMicroelectronics |
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ST10F271 数据表(HTML) 132 Page - STMicroelectronics |
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132 / 173 page  Electrical characteristics ST10F271 132/173 1. VAREF can be tied to ground when A/D Converter is not in use: an extra consumption (around 200µA) on main VDD is added due to internal analogue circuitry not completely turned off: so, it is suggested to maintain the VAREF at VDD level even when not in use, and eventually switch off the A/D Converter circuitry setting bit ADOFF in ADCON register. 2. VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be 0x000H or 0x3FFH, respectively. 3. Not 100% tested, guaranteed by design characterization. 4. During the sample time the input capacitance CAIN can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tS depends on programming and can be taken from Table 67: A/D converter programming. 5. This parameter includes the sample time tS, the time for determining the digital result and the time to load the result register with the conversion result. Values for the conversion clock tCC depend on programming and can be taken from next Table 67. 6. DNL, INL, OFS and TUE are tested at VAREF = 5.0 V, VAGND = 0V, VDD = 5.0 V. It is guaranteed by design characterization for all other voltages within the defined voltage range. ‘LSB’ has a value of VAREF/1024. For Port5 channels, the specified TUE (± 2LSB) is guaranteed also with an overload condition (see IOV specification) occurring on maximum 2 not selected analog input pins of Port5 and the absolute sum of input overload currents on all Port5 analog input pins does not exceed 10 mA. For Port1 channels, the specified TUE is guaranteed when no overload condition is applied to Port1 pins: when an overload condition occurs on maximum 2 not selected analog input pins of Port1 and the input positive overload current on all analog input pins does not exceed 10 mA (either dynamic or static injection), the specified TUE is degraded (± 7LSB). To get the same accuracy, the negative injection current on Port1 pins shall not exceed -1mA in case of both dynamic and static injection. 7. The coupling factor is measured on a channel while an overload condition occurs on the adjacent not selected channels with the overload current within the different specified ranges (for both positive and Analog Input voltage 2) V AIN SR VAGND VAREF V Reference supply current I AREF CC – – 5 1 mA µA Running mode 3) Power Down mode Sample time t S CC 1– µs 4) Conversion time t C CC 3– µs 5) Differential Non Linearity 6) DNL CC –1 +1 LSB No overload Integral Non Linearity 6) INL CC –1.5 +1.5 LSB No overload Offset Error 6) OFS CC –1.5 +1.5 LSB No overload Total unadjusted error 6) TUE CC –2.0 –5.0 –7.0 +2.0 +5.0 +7.0 LSB Port5 Port1 - No overload 3) Port1 - Overload 3) Coupling Factor between inputs 3) 7) K CC –10–6 – On both Port5 and Port1 Input Pin Capacitance 3) 8) CP1 CC –3pF CP2 CC – 4 6 pF Port5 Port1 Sampling Capacitance 3) 8) CS CC –3.5 pF Analog Switch Resistance 3) 8) RSW CC – – 600 1600 W Port5 Port1 RAD CC –1300 W Table 66. A/D converter characteristics Parameter Symbol Limit Values Unit Test Condition min. max. |
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