ST10F271 datasheet(128/173 Pages) STMICROELECTRONICS

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Electrical characteristics

ST10F271

128/173

Port 6 inactive current (P6[4:0]) (6) (7)

IP6H

––40

µAV

OUT = 2.4 V

Port 6 active current (P6[4:0]) (6) (8)

IP6L

–500

–

µAV

OUT = 0.4V

PORT0 configuration current (6)

IP0H

––10

µAV

IN = 2.0V

IP0L

–100

–

µAV

IN = 0.8V

Pin Capacitance (Digital inputs / outputs) CIO CC

–10

(1) (6)

Run Mode Power supply current (9)

(Execution from Internal RAM)

ICC1

–

15 + 1.5

fCPU

–

Run Mode Power supply current (1) (10)

(Execution from Internal Flash)

ICC2

–

15 + 1.5

fCPU

–

Idle mode supply current (11)

IID

–

15 + 0.6

fCPU

–

Power Down supply current (12)

(RTC off, Oscillators off,

Main Voltage Regulator off)

IPD1

–200

µAT

A = 25°C

Power Down supply current (12)

(RTC on, Main Oscillator on,

Main Voltage Regulator off)

IPD2

–

400

Typical

Value

µAT

A = 25°C

Power Down supply current (12)

(RTC on, 32kHz Oscillator on,

Main Voltage Regulator off)

IPD3

–200

µAT

A = 25°C

Stand-by supply current (12)

(RTC off, Oscillators off, VDD off, VSTBY

on)

ISB1

–120

µA

VSTBY = 5.5 V

TA = TJ = 25°C

–500

µA

VSTBY = 5.5 V

TA = TJ = 125°C

Stand-by supply current (12)

(RTC on, 32kHz Oscillator on,

main VDD off, VSTBY on)

ISB2

–120

µA

VSTBY = 5.5 V

TA = TJ = 125°C

–500

µA

VSTBY = 5.5 V

TA = TJ = 125°C

Stand-by supply current (1) (12)

(VDD transient condition)

ISB3

–2.5

–

Not 100% tested, guaranteed by design characterization.

This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float

and the voltage is imposed by the external circuitry.

Port 5 leakage values are granted for not selected A/D Converter channel. One channels is always selected (by default,

after reset, P5.0 is selected). For the selected channel the leakage value is similar to that of other port pins.

The leakage of P2.0 is higher than other pins due to the additional logic (pass gates active only in specific test modes)

implemented on input path. Pay attention to not stress P2.0 input pin with negative overload beyond the specified limits:

failures in Flash reading may occur (sense amplifier perturbation). Refer to next Figure 37: Port2 test mode structure for a

scheme of the input circuitry.

Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the

specified range (i.e. VOV > VDD + 0.3 V or VOV < –0.3 V). The absolute sum of input overload currents on all port pins may

not exceed 50mA. The supply voltage must remain within the specified limits.

This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if they are used

for CS output and the open drain function is not enabled.

Table 63.

DC characteristics (continued)

Parameter

Symbol

Limit values

Unit

Test Condition

min.

max.

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