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STCMB1 数据表(PDF) 47 Page - STMicroelectronics |
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STCMB1 数据表(HTML) 47 Page - STMicroelectronics |
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47 / 59 page ![]() DocID028958 Rev 4 47/59 STCMB1 Application information 59 The operation of the converter in the overload is limited in time by a mechanism based on a pair of internal counters: one is a modulo 128 cyclical counter, clocked by the switching frequency of the LLC, and the other is a modulo 20 K counter, clocked by the internal reference at about 1 MHz. The first OCP1 event (first time Visen_hb 800 mV, typ.) turns on the two counters. If a second OCP1 event occurs within 128 cycles of the LLC from the first OCP1 event, then the cyclical counter is reset and restarted, while the modulo 20 K is left free running on its clock. If no OCP1 event occurs within 128 cycles of the LLC from the last OCP1 events, that is the cyclical, the counter reaches its EoC, then the value of the modulo 20 K counter is decreased of 32 and frozen. The value of the modulo 20 K counter is decreased of 32 and frozen, each time the modulo 128 cyclical counter reaches its EoC (no OCP1 event within 128 cycles of the LLC from the last EoC). When the value of the modulo 20 K counter reaches 0 (because of consecutive decrements), the modulo 128 cyclical counter is reset and stopped. Conversely, when an OCP1 event occurs while the modulo 20 K counter is frozen (OCP1 event occurring within 128 cycles of the LLC from the last EoC), its counting is restarted and the modulo 128 cyclical counter is reset. When the modulo 20 K counter reaches its EoC, a soft-stop procedure is activated (and the counters are reset and stopped). The soft-stop procedure consists of a controlled turn-off of the LLC stage in 128 cycles: the soft-start capacitor is completely discharged to increase the switching frequency so that the energy in the resonant tank is minimized. After the shutdown, the adapter will be driven by the natural discharge and recharge by the HVSU of the VCC pin. If the overload condition is permanent, then the adapter will operate in the hiccup mode. In practice, the modulo 20 K counter will reach its EoC in 20 ms (18 ms min.) in case of the output short-circuit, if the latter does not trigger the OCP2, or when the overload is above a certain current level and/or time length. Waveforms of the converter operation at the first shutdown by the soft-stop procedure and during the hiccup mode are given in Figure 29. Detailed operation is described below Figure 29. Figure 29. Hiccup mode operation during OVL and detail of current limiting |
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