STCMB1 datasheet(23/59 Pages) STMICROELECTRONICS

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STCMB1

Application information

7.7

PFC: error amplifier, regulation loop and VFF

The STCMB1 regulation loop keeps the output voltage regulated by means of a

transconductance amplifier having an internal 2.5 V reference and a typical gain bandwidth

product of 1 MHz. Its inverting input (FB, pin #3) has to be connected to the PFC bulk

capacitor via a resistor divider. Since the voltage on this pin is proportional to the PFC

output voltage, some other monitoring circuitries are connected to this pin. Because of its

high impedance, the FB pin has to be filtered locally by a ceramic capacitor to get a clean

and stable voltage. Typical filtering capacitor values are in the range from some nF up to few

ten nF.

The error amplifier output (COMP, pin #4), offset by -1 V, is then compared with the Ton

ramp signal by the PWM comparator. Thus, the PWM comparator stops the on-time when

VTON = VCOMP - 1 V. The error amplifier output can swing from 1 V (burst mode threshold)

up to 4.5 V (upper value).

The on-time generator delivers a constant current charging an external capacitor connected

to the Ton pin (#5) used to determine the MOSFET on-time each cycle.

To keep the maximum output power deliverable by the PFC almost constant with respect to

the ac input voltage, a two-level, discrete voltage feedforward (VFF) is integrated in the

STCMB1. The ac input voltage is monitored via the HV pin (#1) and the signal is fed into

a peak detector. This information is used to properly set the value of the current ITON

sourced by the TON pin during the normal operation to determine the on-time of the power

switch. The threshold aimed to select the proper value of the current ITON is set between

145 and 160 Vac_rms. The proper operation of the PFC, with the right ITON current, is

guaranteed below 145 Vac_rms and above 160 Vac_rms.

Whereas mains voltage rises are detected immediately, mains voltage drops are detected

after a latency of 16 ms.

Because of this latency, particular attention in the design of the application must be paid to

account for line transients that span across the mains ranges. To avoid that the half-bridge

shuts down due to the dc brown-out function being triggered (see Section 7.16: Dc brown-

out function (HB enable and disable) on page 30), the following relationship has to be

fulfilled:

Equation 10

where:

Cbulk is the output capacitor of the PFC stage.

VOUT is the maximum allowed output voltage drop (the difference between the

regulated output voltage VREG and the dc brown-out threshold

(280 V if VREG = 400 V).

ILOAD = POUT/VREG is the output current delivered by the PFC stage and provided

to the downstream half-bridge.

m s

1 6

Δ V

L O A D

O U T

b u l k

STCMB1 数据表(PDF) 23 Page - STMicroelectronics

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