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STCMB1 数据表(PDF) 54 Page - STMicroelectronics |
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STCMB1 数据表(HTML) 54 Page - STMicroelectronics |
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54 / 59 page  STCMB1 layout hints STCMB1 54/59 DocID028958 Rev 4 13. It is better do avoid the HVG trace under the IC, between pin rows (see Figure 33). This layout solution should be avoided because the high dV/dt of the HV traces might affect the low signal pins. It is a better practice using a suitable SMT package for the bootstrap capacitor and route the HVG track below, as on the right side. The IC and MOSFETs positioning like in the sketch here below on the left should be avoided because the trace length cannot be minimized. Figure 33. Critical (left) and preferred (right) MOSFETs and Cboot routing and placement |
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