STPM098C datasheet(71/110 Pages) STMICROELECTRONICS

71 / 110 page

Regulated output voltage sensing is performed differentially through pins VSEN and VRTN in order to

compensate board and other components parasitic effects. The error between output voltage and the

programmable set point is computed and properly shifted to fit the cascaded ADC dynamic range. Voltage error

combined with drooping voltage from the load-line circuitry is digitized by a high-speed ADC and fed to the digital

controller. The compensator uses a PID with two additional poles to provide the digital equivalent of a type III

analog compensator.

The PWM modulator combines the outputs of the PID and the phase current balancing control to define the ON

time duration for the single phase. The PWM modulator has enough resolution to ensure that there are no limit

cycles.

3.14.1

Open Loop control (OLC)

STPM098C optionally allows to bypass the closed control loop by properly setting a PMBus™ command as

follows:

Table 56. Open loop control configuration bits

OPEN_LOOP_CONFIG<15:0>

Description

OPEN_LOOP_CONFIG<0>

Open loop control enable

OPEN_LOOP_CONFIG<4:1>

Number of active phases

OPEN_LOOP_CONFIG<10:5>

Fine ON time tuning. LSB = 25 ns /64

OPEN_LOOP_CONFIG<15:11>

Coarse ON time tuning. LSB = 25 ns

Once enabled, the open loop control drives the programmed PWM outputs with the fixed programmed frequency

and ON time without any link with actual output voltage and load current.

3.14.2

Phase assignment programming (PSP)

STPM098C controller supports up to 8 phases driving that can be distributed between loop 1 and loop 2 so that:

N+M≤8

M≤4

(27)

Where:

N is the number of phases assigned to the Loop 1.

M is the number of phases assigned to the Loop 2.

Unassigned phases have the related PWM set to HIZ state and ISEN monitor is disabled.

Phase assignment between Loop 1 and Loop 2 can be programmed by a dedicated PMBus™ command as

follows:

Table 57. Phase assignment bits

PHASE_CFG (0x)

Loop 1 active phases

Loop 2 active phases

Loop 1 phase count

Loop 2 phase count

0 (loop disabled)

1-2

1-3

1-4

1-5

1-6

1-7

1-8

1-2

STPM098C

Functional description

DS14440 - Rev 1

page 71/110

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