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STPM098C 数据表(PDF) 40 Page - STMicroelectronics |
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STPM098C 数据表(HTML) 40 Page - STMicroelectronics |
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40 / 110 page  3.6.2 Digital output (DO) Digital output pins on STPM098C are used to transfer an internal digital information to an external voltage domain. Table 27. Digital input pins functional partitioning Pin Default state Description PWMn [n = 1, 2, 3, 4, 5, 6, 7, 8] Type A - Push-pull PWM pins SM_DATA, SM_CLK, SM_ALERT, FAULT, VR_HOT, POWERIN_ALERT, VRRDY1, VRRD2 Type B - Open drain PMBus™ pins and FOR pins Type A digital output allows HIZ state. HIZ state is achieved by switching of pull-up and pull-down sources. No active sources are available on output pin in this state. When unsupplied, type A digital output goes directly in HIZ state. Figure 32. Digital output simplified structures - Type A and B GND B) From Main Logic Output Pin VREF2 GND From Main logic Level Shifter Shoot-through protection V3V3_DIG AND Output Pin A) Table 28. Output electrical characteristics - Type A Symbol Parameter Test condition Min Typ Max Unit Notes DOA_out_hl High output voltage Iload = -1 mA VREF2-0.2 - - V - DOA_out_ll Low output voltage Iload = 1 mA 0 - 0.2 V - DOA_out_hiz_leak Output leakage in HIZ Pin = 1.7 V -5 - 5 uA - T_doa_rt Output rise time Cload = 120 pF from 10% to 70% 5 10 15 ns - T_doa_ft Output fall time Cload = 120 pF from 70% to 10% 5 10 15 ns - Table 29. Output electrical characteristics - Type B Symbol Parameter Test condition Min Typ Max Unit Notes DOB_in_ll Low output voltage Iload = 350 μA - - 0.4 V - T_dob_ft Output fall time Cload = 120 pF from 70% to 10% 8 12.5 16 ns - 3.7 Internal clock Table 30. Internal clock electrical characteristics Symbol Parameter Test condition Min Typ Max Unit Notes CLK_freq System clock frequency CLK_SSM_EN = 0 - 40 - MHz - CLK_freq_acc System clock frequency accuracy CLK_SSM_EN = 0 -5 - +5 % - CLK_freq_match Main vs. auxiliary frequency matching CLK_SSM_EN = 0 -10 - +10 % - STPM098C Functional description DS14440 - Rev 1 page 40/110 |
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