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STPM098C 数据表(PDF) 21 Page - STMicroelectronics |
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STPM098C 数据表(HTML) 21 Page - STMicroelectronics |
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21 / 110 page  – PMBus™ read/write operations are available. If no fault is present and the fault flag is cleared and at least one VRn_EN pin is high the next state is LOOP ON STATE. 7. LOOP ON STATE Internal supply and reference voltage/currents are available and within spec ranges. Main functions: – Input/output telemetry and monitoring units enabled; – Control loop is enabled and PWMn status depends on control logic assessment; – PMBus™ read/write operations are available. 8. RESET STATE Internal supply and reference voltage/currents levels are degraded or shutdown. The main logic is under reset. All functions are disabled: – Input/output telemetry and monitoring units are disabled; – Control loop is disabled and PWMn outputs are in HIZ; – PMBus™ read/write operations are not available. The device persists in this state if POR_DIG = ’0’ (internal signal). Table 14. Device operation modes summary Operation mode Logic core PWMn outputs Telemetry and diagnostic PMBus™ access OFF Reset HIZ Disabled Disabled RESET Reset HIZ Disabled Disabled WAIT POR_ANA REL Functional HIZ Disabled Disabled NVM DWNL Functional HIZ Disabled Disabled BIST Functional HIZ Disabled Disabled LOOP ON Functional Functional/HIZ Enabled Read/Write SAFE STATE Functional HIZ Partially enabled Read/Write LOCKUP STATE Functional HIZ Disabled Disabled 3.3 BIST mode A built-in self-test (BIST) procedure is implemented to check safety relevant circuitries both in digital core and in the analog monitor circuits on STPM098C at each device power-up. The BIST procedure is then divided into memory BIST (MBIST) and analog BIST (ABIST). The purpose of MBIST is to check the integrity of embedded ROM/RAM structures. The purpose of ABIST procedure is to check the correct functionality of analog structures involved in safety relevant monitors and of the safety isolated off path, by detecting stuck or line interruptions on critical signal paths. BIST mode access The BIST mode access state machine flow is based on NVM based register defining the enabling of MBIST and ABIST as follows: Table 15. MBIST activation register MBIST_EN Description 0 MBIST procedure disabled 1 MBIST procedure enabled (default) STPM098C Functional description DS14440 - Rev 1 page 21/110 |
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