STPM098C datasheet(28/110 Pages) STMICROELECTRONICS

28 / 110 page

Figure 16. Latched fault - Permanent fault timing diagram

DRIVE

Fault

Occurrence

FAULT

(PMBus

Flag)

FAULT (pin)

VRRDY (pin)

SM_ALERT

(pin)

VRn_EN

PWMn

Fault persist

Fault appear

Tclear (**)

3Tclk

HiZ

(*)

(*) Signaling Filter Time = Fault Detection + Reaction Time

(**) Tclear is the minimum time VRn_EN shall be asserted LOW for fault clear to be effective

Fault Detection +

Reaction Time

Table 22. VRn_EN clear time electrical characteristics

Symbol

Parameter

Test condition Min Typ Max Unit

Notes

VRn_EN_tclear Minimum time interval to assert a low value on VRn_EN

μs

[n = 1, 2]

3.4.2.2

Latched fault with active pull-down

This fault reaction scenario is intended to reduce the undershoot on the output voltage when recovery from an

overvoltage condition. When an overvoltage fault is detected and the related FHC register is programmed at “11”,

the related PMBus™ flag is set to ‘1’ and related fault redirection pins are asserted low.

Internal logic reacts in first place by setting all PWM output assigned to the loop to ‘0’, then the internal logic

reacts by establishing SAFE_HIZ state if either of the following conditions is verified:

•

VSENn ≤ 0.25 V_th for an interval longer than T_tout_mon_detect_dly

•

ISENn - CFILT/VREF1 ≤ -IOUTm_noc_slow_th

The SAFE_HIZ mode can be left when all the following conditions are met in this sequence:

1. Latched fault is removed.

2. Clear mechanism - One of the following actions, required by application software:

–

VR_EN1/VR_EN2 is asserted low for at least T_clear and then asserted back high.

–

CLEAR_FAULTS command by PMBus™ (clears all faults).

–

Dedicated clear commands by PMBus™ (clears single fault).

STPM098C

Functional description

DS14440 - Rev 1

page 28/110

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