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STPM098C 数据表(PDF) 35 Page - STMicroelectronics

部件名 STPM098C
功能描述  Automotive dual digital 8-phase controller with PMBus™
PDF  110 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STPM098C 数据表(HTML) 35 Page - STMicroelectronics

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Figure 25. Power-up sequence - Slow VCC rise-up
POR_DIG
(internal signal)
VREF1_UV_TH
RESET
PWMn
VCC
VCC_UV_TH
INT_RST
(PMBus flag)
VRn_EN
FULL ON
V
t
VREF1
DRIVE
No PMBus Read/Write Available
No Telemetry and Diagnosis
No Regulation
POR_ANA
(internal signal)
SAFE-HIZ
T_VRn_EN_flt
VREF2
IDLE NVM READ & CRC
T_nvm ≈
7ms
MBIST
LBIST
ABIST
Max 15ms
Max 35ms
Max 1ms
VSENn
VSENn
Soft Start
T_dpor_htol_flt
T_apor_htol_flt
T_diag_rdy
When control loop enable is asserted through VR_ENn pin, for a correct regulation startup a low to high transition
on its input voltage (battery line) shall take place after power-up sequence is completed (that is, after ABIST
completion).
Direct connection of VR_ENn to VCC or VREFn shall be avoided.
Loop enabling/disabling logic is based on VR_ENn voltage level and edge as follows:
VID reference is triggered according to the VR_ENn voltage edge: low to high on VR_ENn enables VID
output as configured in VOUT_COMMAND, high to low transition disables VID output;
The loop controller is triggered according to VR_ENn voltage level: high level on VR_ENn enables loop
controller (except VID), low level disables loop controller.
As a consequence, applying a high logic level to VR_ENn without a clean low to high transition after power-up
(ex. connecting VR_ENn to VREF1) will enable loop controller but not VID reference and will result in output loop
trying to regulate the VID DAC offset.
Table 23. Power-up timings
Symbol
Parameter
Test
condition
Min Typ Max Unit
Notes
T_nvm
NVM data deploy & CRC duration
-
-
7
ms Application information
T_mbist
MBIST procedure duration
-
-
35
ms Application information
T_dbist
DBIST procedure duration
-
-
15
ms Application information
T_abist
ABIST procedure duration
-
-
1
ms Application information
T_diag_rdy
Wait time for VRn_EN rising after PWUP
sequence completion
2
-
-
ms Application information
STPM098C
Functional description
DS14440 - Rev 1
page 35/110



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