STPM098C datasheet(72/110 Pages) STMICROELECTRONICS

72 / 110 page

PHASE_CFG (0x)

Loop 1 active phases

Loop 2 active phases

Loop 1 phase count

Loop 2 phase count

1-3

1-4

1-5

1-6

1-7

7-8

1-2

7-8

1-3

7-8

1-4

7-8

1-5

7-8

1-6

7-8

6-8

1-2

6-8

1-3

6-8

1-4

6-8

1-5

6-8

5-8

1-2

5-8

1-3

5-8

1-4

5-8

Actual active phase number is automatically adjusted by DPS function to optimize phase interleaving for minimum

output ripple. Phase interleaving results in a ripple frequency that is the product of the switching frequency and

the number of phases. A high ripple frequency results in reduced ripple voltage, thereby minimizing the output

filter capacitance requirements, resulting in significant total BOM cost reduction.

For a correct control loop functionality it is of the utmost importance that all assigned phases correspond to a

physical connection at system level (i.e. no assigned phase is unconnected/unused at system level).

3.14.3

Voltage sensing and error calculation

The output voltage sensed at VSENn - VTRNn is subtracted in the analog domain to the corresponding internal

references VID-VID_GND to compute the residual error.

The set-point VID is affected by several PMBus™ command as defined in PMBus™ standard:

•

VOUT_COMMAND

•

VOUT_TRIM

•

VOUT_OFFSET

•

VOUT_MAX

•

VOUT_MARGIN_HIGH

•

VOUT_MARGIN_LOW

The impact of each command can be depicted in the following simplified block diagram:

STPM098C

Functional description

DS14440 - Rev 1

page 72/110

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