ADAR4002ACPZ-R7 datasheet(38/66 Pages) AD

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Data Sheet

ADAR4002

TERMINOLOGY

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Rev. A | 38 of 66

Attenuation

The quantity of attenuation set by the DSA, which is often abbrevi-

ated as ATTN or ATT.

Attenuator

The attenuator is the single DSA unit used in the ADAR4002.

Block Write

A block write is a SPI write to several consecutive registers,

wherein only the address of the first register is clocked in, with

all subsequent consecutive register addresses omitted from the SPI

transaction. See SPI Block Write Mode for more details. Block write

can be used with the StreamWrite registers to significantly reduce

clock cycles.

Data Load Command

The data load command is a command that transfers all TDU and

DSA data from the first rank registers to the second rank registers.

This command is initiated by any DATA_LOAD bit in the DSAxx

registers or in Register 0x98, or with the short control command

using the data load command bits, 0b110.

Digital Stepped Attenuator (DSA)

The DSA is used in the ADAR4002 to set the attenuation.

First Rank Registers

The first rank registers are a set of registers where the SPI data

is initially stored when clocked into the ADAR4002. A data load

command is needed to transfer the TDU and DSA data from the

first rank registers to the second rank registers.

Second Rank Registers

The second rank registers are the second set of registers that hold

the TDU and DSA data, which is applied directly to the TDU and

DSA blocks from these registers. A data load command is needed

to transfer the TDU and DSA data from the first rank registers to the

second rank registers.

Sequencer

The sequencer is a state machine that increments or decrements

the TDU and DSA state one position per update command. The

sequencer sources TDU and DSA data from the second rank

registers and is used in SPI mode only. There are two selectable

sequencers, Sequencer A and Sequencer B.

Sequencer A

Sequencer A is one of the two sequencers that the ADAR4002 fea-

tures. Sequencer A has its own dedicated start and stop sequence

values found in Register 0x10 (SEQUENCERA_START) and Regis-

ter 0x11 (SEQUENCERA_STOP), respectively. Sequencer A has

full access to the second rank register TDU and DSA data.

Sequencer B

Sequencer B is one of the two sequencers that the ADAR4002

features. Sequencer B has its own dedicated start and stop

TDU and DSA state sequence values found in Register 0x12 (SE-

QUENCERB_START) and Register 0x13 (SEQUENCERB_STOP),

respectively. Sequencer B has full access to the second rank

Sequencer Direction

The sequencer direction is the ascension or descension through the

TDU and DSA register addresses that contain the time delay and

attenuation data.

Sequencer Reset Command

The sequencer reset command resets the indicated sequencer to

its start TDU and DSA state.

Shift Register Mode

The shift register mode is one of the two digital modes wherein the

TDU and DSA data is clocked into the first 14-bit shift register using

the CLK_IN and DATA_IO pins, and is then loaded into the second

14-bit shift register by a pulse on the UPDATE pin. Pull the MODE

pin logic high to put the ADAR4002 into shift register mode.

Short Control Command

A short control command is a 6-bit SPI write, initiated by a 0b11

in the first two bits clocked in, that can perform eight unique

actions including sequencer selection, sequencer reset, sequencer

direction, data load command, and an update command. More

information can be found in Figure 7 and Table 4.

SPI Mode

SPI mode is one of the two digital modes wherein the TDU and

DSA data, as well as all the control, is done by the SPI port. Pull the

MODE pin logic low to put the ADAR4002 into SPI mode.

StreamWrite

A StreamWrite is a SPI write to a register or registers between 0x60

and 0x97. These registers contain the same TDU and DSA data

found within Register 0x20 to Register 0x5F; however, the data

flows from one register to the next, which reduces the needed clock

cycles. A change to the TDU and DSA data in Register 0x60 to

0x5F, and vice versa, when the SPI transaction is complete, which

is not to be confused with the block write functionality, which

eliminates the need to clock in the address data after the first

with block write.

Time Delay

The time delay of the ADAR4002 is from RF1 to RF2, either

absolute or normalized. The time delay is varied by the TDU.

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