ADAR4002ACPZ-R7 datasheet(41/66 Pages) AD

41 / 66 page

Data Sheet

ADAR4002

THEORY OF OPERATION

analog.com

Rev. A | 41 of 66

DIGITAL SECTION

The ADAR4002 contains registers for overall control, DSA data,

and TDU data storage. There are two sequencers that can inde-

pendently sequence through the several DSA and TDU states

found in the registers. Each sequencer has its own programmable

start and stop value. The ADAR4002 has two digital modes that the

device can operate in SPI mode or shift register mode. Both modes

are described in the Digital Modes and Interface section.

DIGITAL MODES AND INTERFACE

The ADAR4002 is in SPI mode when the MODE pin is held at logic

low. In SPI mode, the TDU and DSA values are set via the 3-wire or

4-wire SPI bus (the CSB/CLKO, CLK_IN, DATA_IO, and DATA_O

pins). Note that in SPI mode, the CSB/CLKO pin function is the

CSB pin. In addition, the 3-wire SPI does not use the DATA_O pin,

and the DATA_IO becomes a bidirectional data input and output

pin. Two ranks of registers are present, loaded from first rank to

second rank on a data load command, either via a SPI write or

a short control command. Advancing the TDU and DSA state to

the next state using the sequencer is done either with a standard

24-bit SPI write, a 6-bit short control command, or a pulse of the

UPDATE pin. For multiple ADAR4002 chips to share the SPI lines

and enable individual chip control, each chip must have at least its

own dedicated CSB/CLKO, CLK_IN, or DATA_IO line to be unique.

For the fastest parallel data transfer, multiple ADAR4002 chips can

share CSB/CLKO and CLK_IN, with different DATA_IO for each

chip.

When the MODE pin is held at logic high, the ADAR4002 is in

shift register mode. In this mode, the TDU and DSA values are

set via the 2-wire serial interface, with the CLK_IN and DATA_IO

pins, along with the UPDATE pin that serves as the data load

from the first shift register to the second shift register. The output

pins, CSB/CLKO and DATA_O, allow for a daisy-chain connection

of multiple ADAR4002 chips, and the DATA_O pin of one chip

drives the DATA_IO pin of the next chip, and the CSB/CLKO pin

drives the CLK_IN pin of the next chip. Changing the TDU and

DSA to a different state is accomplished by clocking new TDU

and DSA data in on the CLK_IN and DATA_IO pins, and then

strobing the UPDATE pin after the 14th data bit is clocked in. Shift

digital overhead, that is, there are no address bits nor padding

bits, and programs the chips in a serial daisy-chain connection as

shown in Figure 130. The length of this chain is only limited by the

delay through the chain, or the number of clock cycles required to

program all of the ADAR4002 chips.

Figure 126. Digital Block Diagram

ADAR4002ACPZ-R7 数据表(PDF) 41 Page - Analog Devices

ADAR4002ACPZ-R7 数据表(HTML) 41 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

数据表下载