ADAR4002ACPZ-R7 datasheet(43/66 Pages) AD

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Data Sheet

ADAR4002

THEORY OF OPERATION

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The UPDATE bit auto clears on the next CLK_IN edge after being

set, whether in Register 0x99 or via the short control command.

SHIFT REGISTER MODE

In shift register mode, two sets of 14 serially connected, storage

flip-flops allows writing bits during RF activity, without upsetting the

current data applied to the TDU and DSA blocks. A rising edge on

the UPDATE pin loads the bits from the first shift register flip-flops

to the second set, which holds and applies the data to the DSA and

TDU blocks.

This mode offers zero overhead bits for addresses and a minimum

of 14 bits per chip for time delay and attenuation control, but without

any sequencer capability or stored TDU and DSA values (other

than in the two sets of flip-flops). Readback can be done via the

DATA_O pin, which is connected to the output of the 14TH flip-flop

of the first shift register.

The output of one ADAR4002 (CSB_CLKO and DATA_O) can drive

another ADAR4002 (CLK_IN and DATA_IO) directly. Note that,

there is a minimal 2 ns propagation delay between CLK_IN and the

CSB_CLKO and DATA_O outputs. The required number of clock

cycles to set the TDU and DSA data for an individual ADAR4002 is

14 clocks, which is as follows:

►

1 bit for the time delay range

►

7 bits for the time delay

►

6 bits for the DSA attenuation

The total number of clock cycles for N ADAR4002 chips is N x 14

clock cycles. A two chip example is shown in Figure 8. The length

of the chain is only set by the accumulated delay through the chain

or acceptable write length for each write. For simultaneous data

loading, a single update signal to all chips is recommended, with

appropriate delay-matched buffering of the signal as required to

each chip.

See Figure 131 for an example connection schematic in shift

SPI REGISTERS

All configuration registers are detailed in the register summary

(see Table 14). These configuration registers include the standard

Analog Devices SPI setup registers, sequencer setup and readback

registers, start and stop pointers for the sequencer state machines,

and the 32 TDU and DSA states for the sequencers. Table 10

outlines the addresses of each register section.

Table 10. Configuration Register Outline

Start Address

Stop Address

Analog Devices SPI Setup

0x00

0x0F

Sequencer Configuration

0x10

0x18

TDU and DSA Data

0x20

0x5F

StreamWrite TDU and DSA Data

0x60

0x97

Global DATA_LOAD and UPDATE

0x98

0x99

Table 10. Configuration Register Outline (Continued)

Start Address

Stop Address

Second Rank Readback

0xA0

0xDF

TDU and DSA Readback

0xF0

0xF1

The following sections outline some commonly used registers.

The SPI configuration register contains soft-reset functionality (sets

all register values to their default), setup for LSB first bit orientation,

address ascension and descension, and activation of the DATA_O

pin, as follows:

►

Soft reset: Bit 7 and Bit 0

►

LSB first: Bit 6 and Bit 1

►

Address ascension and descension: Bit 5 and Bit 2

►

DATA_O enable and disable: Bit 4 and Bit 3

By default at power-up or on a soft reset, this register is set to

0x3C, which sets the address ascension and enables the DATA_O

pin.

Delay and Attenuation

The time delay control bits are a 7-bit data-word along with a time

delay range selection bit. The time delay range is controlled with Bit

7 set to 0 for standard resolution and a 508 ps maximum time delay

and Bit 7 set to 1 for high resolution and a 254 ps maximum time

delay.

The decoding of the time delay bits (FIRSTRANK_TIMEDELAYxx,

Bits[6:0]) on each time delay register (Register TDxx) is the follow-

ing:

►

Minimum time delay: 0x00

►

Maximum time delay: 0x7F

The attenuator bits (FIRSTRANK_DSAxx, Bits[7:2]) are a 6-bit word

that provides 0.5 dB resolution with 31 dB of attenuation range.

The decoding of the attenuator bits (FIRSTRANK_DSAxx, Bits[7:2])

on each DSA register (Register DSAxx) is the following:

►

Minimum attenuation: 0x00

►

Maximum attenuation: 0x3F

Delay and Attenuation

The ADAR4002 allows a streamwrite of the time delay range selec-

tion bit, the 7-bit time delay value, and the 6-bit DSA attenuation

value, with no extra zero padding bits. This streamwrite functionality

is found in Register 0x60 through Register 0x97. If writing to many

TDU and DSA values at once in SPI block write format and using

the streamwrite registers, repeated address bits as well as excess

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