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ADAR4002ACPZ-R7 数据表(PDF) 53 Page - Analog Devices

部件名 ADAR4002ACPZ-R7
功能描述  0.5 GHz to 19 GHz, 1-Channel, Bidirectional True Time Delay Unit
PDF  66 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADAR4002ACPZ-R7 数据表(HTML) 53 Page - Analog Devices

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Data Sheet
ADAR4002
REGISTER MAP
analog.com
Rev. A | 53 of 66
Table 14. ADAR4002 Register Summary (Continued)
Addr
Name
Bits Bit Name
Description
Reset Access
0x41
DSA16
[7:2] FIRSTRANK_DSA16
6-Bit Attenuation Control. Default = 0x3F, maximum
attenuation.
0x3F
R/W
1
RESERVED
Reserved.
0x0
R
0
DATA_LOAD
Load Signal for Second Rank of Registers. This bit auto
clears after being set.
0x0
R/W
0x42
TD17
7
FR_TDRANGE17
Time Delay Range. 0 = Range 0, 508 ps, and 1 = Range 1,
254 ps.
0x0
R/W
[6:0] FIRSTRANK_TIMEDELAY17
7-Bit Time Delay Control. Default = 0x00, minimum time
delay.
0x0
R/W
0x43
DSA17
[7:2] FIRSTRANK_DSA17
6-Bit Attenuation Control. Default = 0x3F, maximum
attenuation.
0x3F
R/W
1
RESERVED
Reserved.
0x0
R
0
DATA_LOAD
Load Signal for Second Rank of Registers. This bit auto
clears after being set.
0x0
R/W
0x44
TD18
7
FR_TDRANGE18
Time Delay Range. 0 = Range 0, 508 ps, and 1 = Range 1,
254 ps.
0x0
R/W
[6:0] FIRSTRANK_TIMEDELAY18
7-Bit Time Delay Control. Default = 0x00, minimum time
delay.
0x0
R/W
0x45
DSA18
[7:2] FIRSTRANK_DSA18
6-Bit Attenuation Control. Default = 0x3F, maximum
attenuation.
0x3F
R/W
1
RESERVED
Reserved.
0x0
R
0
DATA_LOAD
Load Signal for Second Rank of Registers. This bit auto
clears after being set.
0x0
R/W
0x46
TD19
7
FR_TDRANGE19
Time Delay Range. 0 = Range 0, 508 ps, and 1 = Range 1,
254 ps.
0x0
R/W
[6:0] FIRSTRANK_TIMEDELAY19
7-Bit Time Delay Control. Default = 0x00, minimum time
delay.
0x0
R/W
0x47
DSA19
[7:2] FIRSTRANK_DSA19
6-Bit Attenuation Control. Default = 0x3F, maximum
attenuation.
0x3F
R/W
1
RESERVED
Reserved.
0x0
R
0
DATA_LOAD
Load Signal for Second Rank of Registers. This bit auto
clears after being set.
0x0
R/W
0x48
TD20
7
FR_TDRANGE20
Time Delay Range. 0 = Range 0, 508 ps, and 1 = Range 1,
254 ps.
0x0
R/W
[6:0] FIRSTRANK_TIMEDELAY20
7-Bit Time Delay Control. Default = 0x00, minimum time
delay.
0x0
R/W
0x49
DSA20
[7:2] FIRSTRANK_DSA20
6-Bit Attenuation Control. Default = 0x3F, maximum
attenuation.
0x3F
R/W
1
RESERVED
Reserved.
0x0
R
0
DATA_LOAD
Load Signal for Second Rank of Registers. This bit auto
clears after being set.
0x0
R/W
0x4A
TD21
7
FR_TDRANGE21
Time Delay Range. 0 = Range 0, 508 ps, and 1 = Range 1,
254 ps.
0x0
R/W
[6:0] FIRSTRANK_TIMEDELAY21
7-Bit Time Delay Control. Default = 0x00, minimum time
delay.
0x0
R/W
0x4B
DSA21
[7:2] FIRSTRANK_DSA21
6-Bit Attenuation Control. Default = 0x3F, maximum
attenuation.
0x3F
R/W
1
RESERVED
Reserved.
0x0
R
0
DATA_LOAD
Load Signal for Second Rank of Registers. This bit auto
clears after being set.
0x0
R/W



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