ADAR4002ACPZ-R7 datasheet(13/66 Pages) AD

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Data Sheet

ADAR4002

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. A | 13 of 66

Figure 9. ADAR4002 Pin Configuration

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 3, 8, 10

GND

RF and Analog Ground. Tie all ground pads together to a low impedance plane on the circuit board.

RF1

RF Input or Output Looking into the DSA. Internal DC bias is 0 V. AC coupling is required if the bias of the connected device differs so

that the ADAR4002 internal bias is not disturbed.

V1P0

Digital Supply. Apply 1.0 V.

CLK_IN

Serial Clock Input for Both Digital Modes (1.0 V Logic).

DATA_IO

Dual Direction Pin. DATA_IO is used for both SPI mode and shift register mode. While in the 3-wire SPI protocol, this pin is the serial

data input and output. While in the 4-wire SPI protocol, this pin is the serial data input. While in shift register mode, this pin is the

MODE

Digital Mode Select for Digital Input and Output Data (1.0 V Logic).

If MODE is low (ground), it is in SPI mode, and if MODE is high, it is in shift register mode.

RF2

RF Input or Output Looking into the TDU. Internal DC bias is 0 V. AC coupling is required if the bias of the connected device differs so

that the ADAR4002 internal bias is not disturbed.

V1P2

RF Supply Voltage. Apply 1.2 V.

DATA_O

Serial Data Output for Both Digital Modes. While in the 4-wire SPI protocol, this pin is the serial data output. While in shift register

mode, this pin is the shift register data output (1.0 V logic).

CSB/CLKO

While in SPI mode, chip select (CSB).

While in shift register mode, clock output (1.0 V logic).

UPDATE

While in SPI mode, UPDATE advances the sequencer. While in shift register mode, UPDATE loads data from the shift register to TDU

and DSA (1.0 V logic).

Exposed Pad

RF and Analog Ground. Tie to a low impedance ground plane on the PCB.

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