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ADAR4002ACPZ-R7 数据表(PDF) 55 Page - Analog Devices

部件名 ADAR4002ACPZ-R7
功能描述  0.5 GHz to 19 GHz, 1-Channel, Bidirectional True Time Delay Unit
PDF  66 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADAR4002ACPZ-R7 数据表(HTML) 55 Page - Analog Devices

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Data Sheet
ADAR4002
REGISTER MAP
analog.com
Rev. A | 55 of 66
Table 14. ADAR4002 Register Summary (Continued)
Addr
Name
Bits Bit Name
Description
Reset Access
1
RESERVED
Reserved.
0x0
R
0
DATA_LOAD
Load Signal for Second Rank of Registers. This bit auto
clears after being set.
0x0
R/W
0x58
TD28
7
FR_TDRANGE28
Time Delay Range. 0 = Range 0, 508 ps, and 1 = Range 1,
254 ps.
0x0
R/W
[6:0] FIRSTRANK_TIMEDELAY28
7-Bit Time Delay Control. Default = 0x00, minimum time
delay.
0x0
R/W
0x59
DSA28
[7:2] FIRSTRANK_DSA28
6-Bit Attenuation Control. Default = 0x3F, maximum
attenuation.
0x3F
R/W
1
RESERVED
Reserved.
0x0
R
0
DATA_LOAD
Load Signal for Second Rank of Registers. This bit auto
clears after being set.
0x0
R/W
0x5A
TD29
7
FR_TDRANGE29
Time Delay Range. 0 = Range 0, 508 ps, and 1 = Range 1,
254 ps.
0x0
R/W
[6:0] FIRSTRANK_TIMEDELAY29
7-Bit Time Delay Control. Default = 0x00, minimum time
delay.
0x0
R/W
0x5B
DSA29
[7:2] FIRSTRANK_DSA29
6-Bit Attenuation Control. Default = 0x3F, maximum
attenuation.
0x3F
R/W
1
RESERVED
Reserved.
0x0
R
0
DATA_LOAD
Load Signal for Second Rank of Registers. This bit auto
clears after being set.
0x0
R/W
0x5C
TD30
7
FR_TDRANGE30
Time Delay Range. 0 = Range 0, 508 ps, and 1 = Range 1,
254 ps.
0x0
R/W
[6:0] FIRSTRANK_TIMEDELAY30
7-Bit Time Delay Control. Default = 0x00, minimum time
delay.
0x0
R/W
0x5D
DSA30
[7:2] FIRSTRANK_DSA30
6-Bit Attenuation Control. Default = 0x3F, maximum
attenuation.
0x3F
R/W
1
RESERVED
Reserved.
0x0
R
0
DATA_LOAD
Load Signal for Second Rank of Registers. This bit auto
clears after being set.
0x0
R/W
0x5E
TD31
7
FR_TDRANGE31
Time Delay Range. 0 = Range 0, 508 ps, and 1 = Range 1,
254 ps.
0x0
R/W
[6:0] FIRSTRANK_TIMEDELAY31
7-Bit Time Delay Control. Default = 0x00, minimum time
delay.
0x0
R/W
0x5F
DSA31
[7:2] FIRSTRANK_DSA31
6-Bit Attenuation Control. Default = 0x3F, maximum
attenuation.
0x3F
R/W
1
RESERVED
Reserved.
0x0
R
0
DATA_LOAD
Load Signal for Second Rank of Registers. This bit auto
clears after being set.
0x0
R/W
0x60
STREAMWRITE00
7
FR_TDRANGE00
Time Delay Range. 0 = Range 0, 508 ps, and 1 = Range 1,
254 ps.
0x0
R/W
[6:0] FIRSTRANK_TIMEDELAY00, Bits[6:0] 7-Bit Time Delay Control. Default = 0x00, minimum time
delay.
0x0
R/W
0x61
STREAMWRITE01
[7:2] FIRSTRANK_DSA00
6-Bit Attenuation Control. Default = 0x3F, maximum
attenuation.
0x3F
R/W
1
FR_TDRANGE01
Time Delay Range. 0 = Range 0, 508 ps, and 1 = Range 1,
254 ps.
0x0
R/W
0
FIRSTRANK_TIMEDELAY01, Bit 6
7-Bit Time Delay Control. Default = 0x00, minimum time
delay.
0x0
R/W
0x62
STREAMWRITE02
[7:2] FIRSTRANK_TIMEDELAY01, Bits[5:0] 7-Bit Time Delay Control. Default = 0x00, minimum time
delay.
0x0
R/W



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