ADAR4002ACPZ-R7 datasheet(48/66 Pages) AD

部件名	ADAR4002ACPZ-R7

功能描述	0.5 GHz to 19 GHz, 1-Channel, Bidirectional True Time Delay Unit

PDF	66 Pages

Scroll/Zoom	100%

制造商	AD [Analog Devices]

网页	http://www.analog.com

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48 / 66 page

Data Sheet

ADAR4002

APPLICATIONS INFORMATION

analog.com

Rev. A | 48 of 66

LOGIC VOLTAGES GREATER THAN 1.2 V

Driving CSB/CLKO and DATA_IO to voltages more than 1.2 V,

appreciable current sinks into the pin, especially over temperature

(see Figure 133). Keep voltage drive levels to 1.2 V or lower on

these bidirectional, dual-use pins to avoid high-current draw. The

high-current draw is especially pronounced for the CSB/CLKO pin

in SPI mode. The CSB/CLKO pin idles high between SPI writes;

therefore, high-current draw occurs between SPI writes if the drive

voltage is more than 1.2 V.

The digital input only pins, CLK_IN, MODE, and UPDATE, do not

draw high current when driven with larger voltages than 1.2 V.

However, 1.2 V is still the recommend operational maximum for

these input pins.

Figure 133. CSB Pin Current vs. CSB Pin Voltage Drive Level over Tempera-

ture While in SPI Mode

ADAR4002ACPZ-R7 数据表(PDF) 48 Page - Analog Devices