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ADAR4002ACPZ-R7 数据表(PDF) 50 Page - Analog Devices |
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ADAR4002ACPZ-R7 数据表(HTML) 50 Page - Analog Devices |
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50 / 66 page ![]() Data Sheet ADAR4002 REGISTER MAP analog.com Rev. A | 50 of 66 Table 14. ADAR4002 Register Summary (Continued) Addr Name Bits Bit Name Description Reset Access 0x17 SEQUENCERA_SEQPOINTER [7:5] RESERVED Reserved 0x0 R [4:0] SEQUENCERA_CURRENTVALUE Current Sequencer Pointer of Sequencer A. Read only. 0x0 R 0x18 SEQUENCERB_SEQPOINTER [7:5] RESERVED Reserved 0x0 R [4:0] SEQUENCERB_CURRENTVALUE Current Sequencer Pointer of Sequencer B. Read only. 0x0 R 0x20 TD00 7 FR_TDRANGE00 Time Delay Range. 0 = Range 0, 508 ps, and 1 = Range 1, 254 ps. 0x0 R/W [6:0] FIRSTRANK_TIMEDELAY00, Bits[6:0] 7-Bit Time Delay Control. Default = 0x00, minimum time delay. 0x0 R/W 0x21 DSA00 [7:2] FIRSTRANK_DSA00 6 Bit Attenuation Control. Default = 0x3F, maximum attenuation. 0x3F R/W 1 RESERVED Reserved. 0x0 R 0 DATA_LOAD Load Signal for Second Rank of Registers. This bit auto clears after being set. 0x0 R/W 0x22 TD01 7 FR_TDRANGE01 Time Delay Range. 0 = Range 0, 508 ps, and 1 = Range 1, 254 ps. 0x0 R/W [6:0] FIRSTRANK_TIMEDELAY01 7-Bit Time Delay Control. Default = 0x00, minimum time delay. 0x0 R/W 0x23 DSA01 [7:2] FIRSTRANK_DSA01 6-Bit Attenuation Control. Default = 0x3F, maximum attenuation. 0x3F R/W 1 RESERVED Reserved. 0x0 R 0 DATA_LOAD Load Signal for Second Rank of Registers. This bit auto clears after being set. 0x0 R/W 0x24 TD02 7 FR_TDRANGE02 Time Delay Range. 0 = Range 0, 508 ps, and 1 = Range 1, 254 ps. 0x0 R/W [6:0] FIRSTRANK_TIMEDELAY02 7-Bit Time Delay Control. Default = 0x00, minimum time delay. 0x0 R/W 0x25 DSA02 [7:2] FIRSTRANK_DSA02 6-Bit Attenuation Control. Default = 0x3F, maximum attenuation. 0x3F R/W 1 RESERVED Reserved. 0x0 R 0 DATA_LOAD Load Signal for Second Rank of Registers. This bit auto clears after being set. 0x0 R/W 0x26 TD03 7 FR_TDRANGE03 Time Delay Range. 0 = Range 0, 508 ps, and 1 = Range 1, 254 ps. 0x0 R/W [6:0] FIRSTRANK_TIMEDELAY03 7-Bit Time Delay Control. Default = 0x00, minimum time delay. 0x0 R/W 0x27 DSA03 [7:2] FIRSTRANK_DSA03 6-Bit Attenuation Control. Default = 0x3F, maximum attenuation. 0x3F R/W 1 RESERVED Reserved. 0x0 R 0 DATA_LOAD Load Signal for Second Rank of Registers. This bit auto clears after being set. 0x0 R/W 0x28 TD04 7 FR_TDRANGE04 Time Delay Range. 0 = Range 0, 508 ps, and 1 = Range 1, 254 ps. 0x0 R/W [6:0] FIRSTRANK_TIMEDELAY04 7-Bit Time Delay Control. Default = 0x00, minimum time delay. 0x0 R/W 0x29 DSA04 [7:2] FIRSTRANK_DSA04 6-Bit Attenuation Control. Default = 0x3F, maximum attenuation. 0x3F R/W 1 RESERVED Reserved. 0x0 R 0 DATA_LOAD Load Signal for Second Rank of Registers. This bit auto clears after being set. 0x0 R/W 0x2A TD05 7 FR_TDRANGE05 Time Delay Range. 0 = Range 0, 508 ps, and 1 = Range 1, 254 ps. 0x0 R/W |
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