ADAR4002ACPZ-R7 datasheet(42/66 Pages) AD

42 / 66 page

Data Sheet

ADAR4002

THEORY OF OPERATION

analog.com

Rev. A | 42 of 66

SPI TRANSACTION PROTOCOLS

The ADAR4002 in SPI mode provides three different possible SPI

transaction protocols, which include the following:

►

Standard Analog Devices, Inc., 24-bit SPI write and read proto-

cols

►

SPI block write and read mode

►

Short control command

These first two protocols follow the Analog Devices standard 16-bit

address header followed by an 8-bit data-word, or several consecu-

tive 8-bit data-words for the SPI block write and read mode. These

two protocols are used for all writes to the registers. Note that

for 4-wire SPI readback on the DATA_O pin, DATA_O must be

enabled by setting Bits[4:3] high in Register 0x00. Otherwise, the

ADAR4002 is in 3-wire SPI mode with Bits[4:3] low in Register

0x00. By default upon power-up, the ADAR4002 is in 4-wire SPI

mode. Timing diagrams for the Analog Devices SPI mode are

shown in Figure 2 through Figure 6. The register map is shown in

Table 14.

Short control commands are initiated by unique values set on

the first two bits that are clocked in on the SPI and make the

transaction length 6 bits. If the first two data bits are 0b11 and

the SPI transaction is 6 bits in length, this command is recognized

as a short control command. Following the leading 0b11 bits, the

decoding structure of the short control command is shown in Table

SPI MODE

In SPI mode, registers provide storage of up to 32 TDU and DSA

states. There are two sequencer state machines (Sequencer A and

Sequencer B) that allow the user to sequentially step through the

32 states. The sequencers are independent of each other, each

having separate start and stop values, as well as a sequence

direction. The user can switch between the sequencers, change

direction on either sequencer, or reset either sequencer to its start

value at any time using a SPI write or short control command.

Two ranks of registers store the TDU and DSA data. The sequenc-

ers source their data from the second rank registers, which allows

the data in the first rank registers to be completely rewritten while

simultaneously sequencing through the second rank register data.

This dual-rank, two sequencer setup is flexible and ideal for situa-

tions with a set of transmit TDU and DSA values and a set of

receive TDU and DSA values, as well as for situations in which

the user wants to write a future set of TDU and DSA values while

simultaneously sequencing through a previously written set.

Figure 127. Sequencer State Machine Block Diagram

DATA LOAD

All the TDU and DSA data (the 32 TDU and DSA states) from

the first rank registers are loaded to the second rank registers

by asserting any DATA_LOAD bit in each DSA register (Bit 0)

or in Register 0x98, or by using the short control command. The

DATA_LOAD bit automatically clears on the next CLK_IN edge

after being set in any of the DSA registers, Register 0x98, or if

accomplished with a short control command.

The active edge for the DATA_LOAD command is the next rising

edge of CLK_IN following the assertion of the DATA_LOAD bit.

If a DATA_LOAD command is to be immediately followed by an

update using the UPDATE pin, an extra clock cycle must be added

after the DATA_LOAD bit is asserted, to ensure the DATA_LOAD

command has taken effect before the update rising edge. The extra

clock cycle can be while the CSB/CLKO is low or high. If the next

command is any SPI transaction, no extra SPI clock is necessary.

UPDATE

While in SPI mode, to apply TDU and DSA data from the second

rank registers to the actual TDU and DSA blocks, an update

command is required, which applies whether the user is initially

loading the TDU and DSA state that corresponds to the sequencer

start value or advancing the sequencer to its next TDU and DSA

state.

An update command is accomplished by asserting the UPDATE bit

in Register 0x99, using the update short control command or by a

rising edge (low-to-high) on the UPDATE pin.

The active edge that triggers the loading of the TDU and DSA state

from the second rank registers to the TDU and DSA blocks varies.

If issuing an update command with a regular SPI write, the active

edge is the eighth CLK_IN rising edge on the eighth data bit. The

active edge on an update short control command is the CSB/CLKO

rising edge, which completes the command. The active edge on the

UPDATE pin is any rising edge.

ADAR4002ACPZ-R7 数据表(PDF) 42 Page - Analog Devices

ADAR4002ACPZ-R7 数据表(HTML) 42 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

数据表下载