ADAR4002ACPZ-R7 datasheet(45/66 Pages) AD

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Data Sheet

ADAR4002

APPLICATIONS INFORMATION

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Rev. A | 45 of 66

BASIC CONNECTIONS

The ADAR4002 has two power supply domains: a 1.2 V supply

for the RF and analog circuitry and an 1.0 V supply for the digital

blocks. These power supply domains must be decoupled to ground

as shown in Figure 128.

There are only two RF pins: RF1 and RF2 (Pin 2 and Pin 9,

respectively). These pins are matched to 50 Ω and thus must be

connected to a transmission line with a characteristic impedance of

50 Ω. The RFx pins each have a pair of ground pins surrounding

them, which creates a ground-signal-ground type connection, mak-

ing it simple to interface with PCB transmission lines. RF1 and RF2

must be AC-coupled so that their internal bias is not disturbed.

The MODE pin controls the state of the digital mode of the partA-

DAR4002 as follows:

►

When MODE is pulled to ground, the ADAR4002 is in SPI mode.

►

When MODE is pulled to 1 V, the ADAR4002 is in shift register

mode.

The CLK_IN, CSB/CLKO, DATA_IO, and DATA_O constitute the

SPI or shift register pins. When in SPI mode, the functions of these

pins are as follows:

►

CLK_IN is the SPI clock input.

►

CSB/CLKO is the: SPI chip select input.

►

DATA_IO is the SPI data input only in a 4-wire SPI protocol, or

the SPI data input and output in a 3-wire SPI protocol.

►

DATA_O is the SPI data output in a 4-wire SPI protocol.

Note that the ADAR4002 has no device address pins, so to share

SPI lines and allow individual control, each ADAR4002 must have

its own dedicated CSB/CLKO line, CLK_IN line, or DATA_IO line,

to be individually addressed while in SPI mode (see Figure 129).

For the fastest, parallel data transfer, multiple ADAR4002 chips

can share CSB/CLKO and CLK_IN with different DATA_IO for each

chip.

When the ADAR4002 is in shift register mode, the functions of

these pins are as follows:

►

CLK_IN is the clock input.

►

CSB_CLKO is the clock output.

►

DATA_IO is the data input.

►

DATA_O is the data output.

The shift register allows the user to daisy-chain several ADAR4002

chips together. A single shift register write can contain all the DSA

and TDU data of the daisy-chained chips. This setup is shown in

Figure 131.

The UPDATE pin advances the sequencer to the next DSA and

TDU value if in SPI mode or loads the DSA and TDU data if in shift

All digital pins can be driven to 1.2 V without any issues. For

additional information, see the Logic Voltages Greater Than 1.2 V

section.

Figure 128. Basic Connection in SPI Mode

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