ADAR4002ACPZ-R7 datasheet(40/66 Pages) AD

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Data Sheet

ADAR4002

THEORY OF OPERATION

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Rev. A | 40 of 66

RF PATH

The ADAR4002 is a low power, broadband, bidirectional, single-

channel IC for use in applications requiring programmable time

delay and/or attenuation. Both the RF1 and RF2 ports are internally

matched to 50 Ω. The ADAR4002 is intended to operate over a

frequency range of 2 GHz to 18 GHz, but the device can operate

down to 500 MHz and up to 19 GHz with limited degradation in

performance. The DSA is connected to the RF1 port, while RF2 is

connected to the TDU. Driving the RF1 port allows improved P1dB

performance vs. DSA code, relative to driving RF2. See the Typical

Performance Characteristics section for more detail.

TDU AND DSA

The TDU has 7-bit resolution, with two selectable time delay rang-

es, 508 ps and 254 ps, which creates step sizes of 4 ps and 2 ps,

respectively. Time Delay Range 0 is recommended for applications

extending down to 2 GHz where 508 ps of time delay provides

approximately 365° of phase shift. While Time Delay Range 1 is

recommended for applications 4 GHz and above, where 254 ps of

time delay provides 365° of phase shift at 4 GHz. Range 1 also

provides less loss relative to Range 0, which is advantageous as

the ADAR4002 insertion loss increases with frequency. Table 9

shows a summary of the time delay control.

Table 9. Time Delay Control Summary

Range

Maximum Time Delay

Step Size

508 ps

4 ps

254 ps

2 ps

The DSA has 6-bit resolution with an attenuation range of 31.5 dB

and step size of 0.5 dB.

The DSA and TDU are digitally controlled by either the register and

on-chip sequencers (SPI mode) or the shift register mode. Both

modes clock data into and out of the chip via a shared set of digital

pins. The MODE pin controls the digital mode of the chip. See the

Digital Section for more details.

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