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ADAR4002ACPZ-R7 数据表(PDF) 54 Page - Analog Devices

部件名 ADAR4002ACPZ-R7
功能描述  0.5 GHz to 19 GHz, 1-Channel, Bidirectional True Time Delay Unit
PDF  66 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADAR4002ACPZ-R7 数据表(HTML) 54 Page - Analog Devices

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Data Sheet
ADAR4002
REGISTER MAP
analog.com
Rev. A | 54 of 66
Table 14. ADAR4002 Register Summary (Continued)
Addr
Name
Bits Bit Name
Description
Reset Access
0x4C
TD22
7
FR_TDRANGE22
Time Delay Range. 0 = Range 0, 508 ps, and 1 = Range 1,
254 ps.
0x0
R/W
[6:0] FIRSTRANK_TIMEDELAY22
7-Bit Time Delay Control. Default = 0x00, minimum time
delay.
0x0
R/W
0x4D
DSA22
[7:2] FIRSTRANK_DSA22
6-Bit Attenuation Control. Default = 0x3F, maximum
attenuation.
0x3F
R/W
1
RESERVED
Reserved.
0x0
R
0
DATA_LOAD
Load Signal for Second Rank of Registers. This bit auto
clears after being set.
0x0
R/W
0x4E
TD23
7
FR_TDRANGE23
Time Delay Range. 0 = Range 0, 508 ps, and 1 = Range 1,
254 ps.
0x0
R/W
[6:0] FIRSTRANK_TIMEDELAY23
7-Bit Time Delay Control. Default = 0x00, minimum time
delay.
0x0
R/W
0x4F
DSA23
[7:2] FIRSTRANK_DSA23
6-Bit Attenuation Control. Default = 0x3F, maximum
attenuation.
0x3F
R/W
1
RESERVED
Reserved.
0x0
R
0
DATA_LOAD
Load Signal for Second Rank of Registers. This bit auto
clears after being set.
0x0
R/W
0x50
TD24
7
FR_TDRANGE24
Time Delay Range. 0 = Range 0, 508 ps, and 1 = Range 1,
254 ps.
0x0
R/W
[6:0] FIRSTRANK_TIMEDELAY24
7-Bit Time Delay Control. Default = 0x00, minimum time
delay.
0x0
R/W
0x51
DSA24
[7:2] FIRSTRANK_DSA24
6-Bit Attenuation Control. Default = 0x3F, maximum
attenuation.
0x3F
R/W
1
RESERVED
Reserved.
0x0
R
0
DATA_LOAD
Load Signal for Second Rank of Registers. This bit auto
clears after being set.
0x0
R/W
0x52
TD25
7
FR_TDRANGE25
Time Delay Range. 0 = Range 0, 508 ps, and 1 = Range 1,
254 ps.
0x0
R/W
[6:0] FIRSTRANK_TIMEDELAY25
7-Bit Time Delay Control. Default = 0x00, minimum time
delay.
0x0
R/W
0x53
DSA25
[7:2] FIRSTRANK_DSA25
6-Bit Attenuation Control. Default = 0x3F, maximum
attenuation.
0x3F
R/W
1
RESERVED
Reserved.
0x0
R
0
DATA_LOAD
Load Signal for Second Rank of Registers. This bit auto
clears after being set.
0x0
R/W
0x54
TD26
7
FR_TDRANGE26
Time Delay Range. 0 = Range 0, 508 ps, and 1 = Range 1,
254 ps.
0x0
R/W
[6:0] FIRSTRANK_TIMEDELAY26
7-Bit Time Delay Control. Default = 0x00, minimum time
delay.
0x0
R/W
0x55
DSA26
[7:2] FIRSTRANK_DSA26
6-Bit Attenuation Control. Default = 0x3F, maximum
attenuation.
0x3F
R/W
1
RESERVED
Reserved.
0x0
R
0
DATA_LOAD
Load Signal for Second Rank of Registers. This bit auto
clears after being set.
0x0
R/W
0x56
TD27
7
FR_TDRANGE27
Time Delay Range. 0 = Range 0, 508 ps, and 1 = Range 1,
254 ps.
0x0
R/W
[6:0] FIRSTRANK_TIMEDELAY27
7-Bit Time Delay Control. Default = 0x00, minimum time
delay.
0x0
R/W
0x57
DSA27
[7:2] FIRSTRANK_DSA27
6-Bit Attenuation Control. Default = 0x3F, maximum
attenuation.
0x3F
R/W



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