SSM3582ACPZ-R7 datasheet(26/58 Pages) AD

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SSM3582A

Data Sheet

Rev. A | Page 26 of 58

POWER-UP SEQUENCE

Using Only PVDD as a Source

When SSM3582A is used in single-supply mode, all internal rails

are generated from PVDD. The internal AVDD (5 V) and

DVDD (1.8 V) regulators can be enabled by pulling the

AVDD_EN and DVDD_EN pins high. AVDD_EN is pulled to

PVDD, and DVDD_EN is pulled to AVDD. The amplifier is

operational and responds to I2C writes 10 ms after applying

PVDD ≥ 5 V.

Using PVDD and External AVDD

Take care when an external 5 V is supplied to AVDD. The internal

5 V LDO regulator must be disabled by pulling the AVDD_EN pin

low. In this case, DVDD (1.8 V) is generated from PVDD. It is

important to maintain PVDD > AVDD to prevent the back

powering of PVDD.

Using PVDD and External AVDD and DVDD

If using an external AVDD and DVDD source, both the

AVDD_EN and DVDD_EN pins must be pulled low. It is

important to maintain PVDD > AVDD or DVDD to prevent

back powering PVDD.

DVDD must be present for the device to respond to I2C

commands. The device becomes operational ~10 ms after

DVDD is present. PVDD must be at least 5 V for the output

stage to turn on, and must be 6 V for optimal performance.

POWER-DOWN OPERATION

The SSM3582A offers several power-down options via the I2C.

power-down modes.

When set to 1, the SPWDN bit fully powers down the device. In

this case, only the I2C and 1.8 V regulator blocks, if enabled via

the DVDD_EN pin, are kept active.

The SSM3582A monitors both the BCLK and FSYNC pins for

clock presence. When no BCLK is present, the device automa-

tically powers down all internal circuitry to its lowest power

state. When BCLK returns, the device automatically powers up

following its usual power sequence. To guarantee click and pop

free shutdown, power down the device via the SPDWN control

before clock removal.

If enabled, the APWDN_EN bit activates a low power state

after 2048 consecutive zero input samples are received. Only

the I2C and digital audio input blocks are kept active.

Individual channels can be powered down using Bits[3:2] in

The temperature sense ADC can be powered down using Bit 5

in Register 0x04.

CLOCKING

A BCLK signal must be provided to the SSM3582A for proper

operation. The BCLK signal must have a minimum frequency

of 2.048 MHz. The BCLK rate is autodetected, but the sampling

frequency must be indicated. The BCLK rates supported at

32 kHz to 48 kHz are 50, 64, 100, 128, 192, 200, 256, 384, 400,

512, 768, 800, and 1024 times the sample rate.

DIGITAL AUDIO SERIAL INTERFACE

The SSM3582A includes a standard serial audio interface that is

slave only. The interface is capable of receiving I2S, left justified,

PCM, or TDM formatted data.

The serial interfaces have three main operating modes. The stereo

modes, typically I2S or left justified, are used when there is a

single chip on the interface bus. TDM mode is more flexible

and offers the ability to have multiple chips on the bus.

Stereo Operating Modes—I2S, Left Justified

Stereo modes use both edges of FSYNC to determine the

placement of data. Stereo mode is enabled when SAI_MODE = 0,

and the I2S or left justified format is determined by the SDATA_

FMT register setting.

The I2S or left justified interface formats supports various BCLK/

FSYNC ratios (see Table 13). Sample rates from 8 kHz to 192 kHz

are accepted.

TDM Operating Mode

The TDM operating mode allows multiple chips to connect to a

single serial interface.

The FSYNC signal operates at the desired sample rate. A rising

edge of the FSYNC signal indicates the start of a new frame. For

proper operation, this signal must be one BCLK cycle wide, trans-

itioning on a falling BCLK edge. The MSB of data is present on the

SDATA signal one BCLK cycle later. The SDATA signal is

latched on a rising edge of BCLK.

Each chip on the TDM bus can occupy 16, 24, 32, 48, or 64 BCLK

cycles, set via the TDM_BCLKS control bits. The maximum

number of devices connected to a single TDM bus depends on

the sample rate and number of bits per channel. The supported

combinations of sample rates and bit depths are described in

Table 13.

The maximum bit clock frequency is 49.152 MHz. Using the

TDM16 format, up to eight devices (16 channels) can be connected

to a single TDM interface, and can operate at up to a 96 kHz

sample rate and at 32 bits per channel. See Table 13 for the

supported options at the 48 kHz, 96 kHz, and 192 kHz sample

rates. Note that the interface is slave only, with the bit clock,

frame sync, and data provided to the device.

ADDRx pin settings dictate the default TDM slots for each device,

and can be modified using the TDM_SLOT_x control register.

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